Switching Characteristics over Commercial and Industrial Operating Ranges
Write Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
Symbol Description
General Timing Responses
40 MHz
Min
50 MHz
Min
No.
Max
Max Unit
3
4
tCHSV
tCLSH
tCLAV
tCLDV
tCHDX
tCHLH
tLHLL
Status Active Delay
Status Inactive Delay
AD Address Valid Delay
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
0
0
0
0
0
12
12
12
12
0
0
0
0
0
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
5
7
8
9
12
10
tCLCL–5=20
10
15
11
12
13
14
16
tCHLL
tAVLL
ALE Inactive Delay
12
10
ns
ns
ns
ns
ns
AD Address Valid to ALE Low(a)
AD Address Hold from ALE Inactive(a)
AD Address Valid to Clock High
MCS/PCS Active Delay
tCLCH
tCHCL
0
tCLCH
tCHCL
0
tLLAX
tAVCH
tCLCSV
0
0
12
10
MCS/PCS Hold from Command
Inactive(a)
tCLCH
tCLCH
17
tCXCSX
ns
0
0
0
0
0
5
18
19
20
23
tCHCSX MCS/PCS Inactive Delay
12
12
10
10
ns
ns
ns
ns
tDXDL
tCVCTV
tLHAV
DEN Inactive to DT/R Low(a)
Control Active Delay 1(b)
ALE High to Address Valid
0
7.5
Write Cycle Timing Responses
0
0
30
31
tCLDOX
tCVCTX
tWLWH
tWHLH
tWHDX
Data Hold Time
Control Inactive Delay(b)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
2tCLCL–10=40
tCLCH–2
tCLCL–10=15
tCLCH
0
12
10
35
32
WR Pulse Width
33
WR Inactive to ALE High(a)
Data Hold after WR(a)
tCLCH–2
12
34
35
tWHDEX WR Inactive to DEN Inactive(a)
tAVWL A Address Valid to WR Low
tCHCSV CLKOUTA High to LCS/UCS Valid
tCLCH
tCLCL+tCHCL–1.25
0
tCLCL+tCHCL–1.25
65
0
67
12
10
12
10
10
10
0
0
68
tCHAV
tAVBL
CLKOUTA High to A Address Valid
A Address Valid to WHB, WLB Low
tCHCL–1.25
tCHCL–1.25
87
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
b
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
74
Am186TMER and Am188TMER Microcontrollers Data Sheet
AMD [ AMD ]
