Switching Characteristics over Commercial and Industrial Operating Ranges
Read Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
Symbol Description
General Timing Requirements
25 MHz
Min
33 MHz
Min
No.
Max
Max Unit
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold(c)
10
3
8
3
ns
ns
General Timing Responses
3
4
tCHSV
tCLSH
tCLAV
tCLDV
tCHDX
tCHLH
tLHLL
Status Active Delay
Status Inactive Delay
AD Address Valid Delay
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
0
0
0
0
0
20
20
20
20
0
0
0
0
0
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
5
7
8
9
20
15
tCLCL–10=30
tCLCL–10=20
10
11
12
13
14
15
16
tCHLL
tAVLL
tLLAX
tAVCH
tCLAZ
ALE Inactive Delay
20
15
ns
ns
ns
ns
ns
ns
AD Address Valid to ALE Low(a)
AD Address Hold from ALE Inactive(a)
AD Address Valid to Clock High
AD Address Float Delay
tCLCH
tCHCL
0
tCLCH
tCHCL
0
tCLAX=0
0
tCLAX=0
0
20
20
15
15
tCLCSV MCS/PCS Active Delay
MCS/PCS Hold from Command
Inactive(a)
tCHCSX MCS/PCS Inactive Delay
tDXDL
DEN Inactive to DT/R Low(a)
tCLCH
tCLCH
17
tCXCSX
ns
0
0
0
0
18
19
20
21
22
23
20
15
ns
ns
ns
ns
ns
ns
tCVCTV Control Active Delay 1(b)
20
20
20
15
15
15
0
0
0
0
tCVDEX DEN Inactive Delay
tCHCTV Control Active Delay 2(b)
0
0
15
10
tLHAV
ALE High to Address Valid
Read Cycle Timing Responses
0
0
24
25
tAZRL
tCLRL
tRLRH
tCLRH
tRHLH
tRHAV
tRHDX
tAVRL
AD Address Float to RD Active
RD Active Delay
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
20
20
15
15
2tCLCL–15=65
2tCLCL–15=45
26
RD Pulse Width
0
0
27
RD Inactive Delay
28
RD Inactive to ALE High(a)
RD Inactive to AD Address Active(a)
RD High to Data Hold on AD Bus(c)
A Address Valid to RD Low
tCLCH–3
tCLCH–3
tCLCL–10=30
tCLCL–10=20
29
0
0
59
2tCLCL–15=65
2tCLCL–15=45
66
0
0
0
0
67
tCHCSV CLKOUTA High to LCS/UCS Valid
tCHAV CLKOUTA High to A Address Valid
20
20
15
15
68
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
b
c
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
70
Am186TMER and Am188TMER Microcontrollers Data Sheet
AMD [ AMD ]
