P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Reset and Bus Hold (20 MHz and 25 MHz)
Preliminary
Parameter
Description
Reset and Bus Hold Timing Requirements
20 MHz
Min
25 MHz
Min Max Unit
No. Symbol
Max
5
tCLAV
tCLAZ
AD Address Valid Delay and BHE
AD Address Float Delay
0
0
25
25
0
0
20
20
ns
ns
ns
ns
15
57
58
tRESIN RES Setup Time
tHVCL
HOLD Setup(a)
10
10
10
10
Reset and Bus Hold Timing Responses
62
63
64
tCLHAV HLDA Valid Delay
tCHCZ Command Lines Float Delay
tCHCV
0
25
25
25
0
20
20
20
ns
ns
ns
Command Lines Valid Delay
(after Float)
Reset and Bus Hold (33 MHz and 40 MHz)
Preliminary
33 MHz 40 MHz
Min Max Unit
Parameter
No. Symbol
Description
Min
Max
Reset and Bus Hold Timing Requirements
5
tCLAV
tCLAZ
AD Address Valid Delay and BHE
AD Address Float Delay
0
0
8
8
15
15
0
12
12
ns
ns
ns
ns
15
57
58
0
5
5
tRESIN RES Setup Time
tHVCL
HOLD Setup(a)
Reset and Bus Hold Timing Responses
62
63
64
tCLHAV HLDA Valid Delay
tCHCZ Command Lines Float Delay
tCHCV
0
15
15
15
0
12
12
12
ns
ns
ns
Command Lines Valid Delay
(after Float)
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.45 V and VIH=2.4 V, except at X1 where VIH=VCC– 0.5 V.
a
This timing must be met to guarantee recognition at the next clock.
Am186/188ES and Am186/188ESLV Microcontrollers
95
AMD [ AMD ]
