P R E L I M I N A R Y
BUS OPERATION
The industry-standard 80C186 and 80C188 microcon-
trollers use a multiplexed address and data (AD) bus.
The address is present on the AD bus only during the
t1 clock phase. The Am186ED/EDLV microcontrollers
continue to provide the multiplexed AD bus and, in ad-
dition, provides a nonmultiplexed address (A) bus. The
A bus provides an address to the system for the com-
plete bus cycle (t1–t4).
for all accesses, thus preserving the industry-standard
80C186 and 80C188 microcontrollers’ multiplexed ad-
dress bus and providing support for existing emulation
tools.
The following diagrams show the bus cycles of the
Am186ED/EDLV microcontrollers when the address
bus disable feature is in effect:
Figure 4 shows the affected signals during a normal
read or write operation for 16-bit mode. The address
and data are multiplexed onto the AD bus.
For systems where power consumption is a concern, it
is possible to disable the address from being driven on
the AD bus during the normal address portion of the
bus cycle for accesses to RAS0, RAS1, UCS, and/or
LCS address spaces. In this mode, the affected bus is
placed in a high-impedance state during the address
portion of the bus cycle. This feature is enabled
through the DA bits in the UMCS and LMCS registers.
When address disable is in effect, the number of sig-
nals that assert on the bus during all normal bus cycles
to the associated address space is reduced, decreas-
ing power consumption and reducing processor switch-
ing noise. In 8-bit mode, the address is driven on
AD15–AD8 during the data portion of the bus cycle re-
gardless of the setting of the DA bits.
Figure 5 shows a 16-bit mode bus cycle when address
bus disable is in effect. This results in the AD bus oper-
ating in a nonmultiplexed address/data mode. The A
bus has the address during a read or write operation.
Figure 6 shows the affected signals during a normal
read or write operation for 8-bit mode. The multiplexed
address/data mode is compatible with the 80C186 and
80C188 microcontrollers and might be used to take ad-
vantage of existing logic or peripherals.
Figure 7 shows an 8-bit mode bus cycle when address
bus disable is in effect. The address and data are not
multiplexed. The AD7–AD0 signals have only data on
the bus, while the AD bus has the address during a
read or write operation.
If the ADEN pin is pulled Low during processor reset,
the value of the DA bits in the UMCS and LMCS regis-
ters is ignored and the address is driven on the AD bus
t1
t2
t3
Data
Phase
t4
Address
Phase
CLKOUTA
A19–A0
Address
AD15–AD0
(Read)
Address
Data
AD15–AD0
(Write)
Address
Data
LCS or UCS
or
MCSx, PCSx
Note: For a detailed description of DRAM control signals, see DRAM switching characteristics
beginning on page 70.
Figure 4. 16-Bit Mode—Normal Read and Write Operation
34
Am186ED/EDLV Microcontrollers
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