D A T A S H E E T
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
t
ACC
t
CE
CE#
t
CH
t
OE
OE#
WE#
t
tDF
OH
OEH
t
High Z
High Z
DQ7
Valid Data
Complement
Complement
Status Data
True
DQ0–DQ6
Valid Data
Status Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
ACC
VA
VA
VA
t
t
CE
t
CH
t
OE
OE#
WE#
t
tDF
OH
OEH
t
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
t
BUS
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
34
Am29SL800D
27546A6 January 23, 2007
AMD [ AMD ]
