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A800DB90PF 参数 Datasheet PDF下载

A800DB90PF图片预览
型号: A800DB90PF
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 1一M× 8位/ 512的K× 16位) CMOS 1.8伏只超低电压闪存 [8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory]
分类和应用: 闪存
文件页数/大小: 46 页 / 1066 K
品牌: AMD [ AMD ]
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D A T A S H E E T  
words. Refer to Word/Byte Configuration‚ on page 8  
for more information.  
The device also enters the standby mode when the  
RESET# pin is driven low. Refer to the next section,  
RESET#: Hardware Reset Pin.  
The device features an Unlock Bypass mode to facili-  
tate faster programming. Once the device enters the  
Unlock Bypass mode, only two write cycles are  
required to program a word or byte, instead of four. The  
Word/Byte Program Command Sequence‚ on page 15  
has details on programming data to the device using  
both standard and Unlock Bypass command  
sequences.  
If the device is deselected during erasure or program-  
ming, the device draws active current until the  
operation is completed.  
I
in Table 7 on page 25 represents the standby  
CC3  
current specification.  
Automatic Sleep Mode  
An erase operation can erase one sector, multiple sec-  
tors, or the entire device. Tables 2 and 3 indicate the  
address space that each sector occupies. A “sector  
address” consists of the address bits required to  
uniquely select a sector. The Command Definitions‚ on  
page 14 has details on erasing a sector or the entire  
chip, or suspending/resuming the erase operation.  
The automatic sleep mode minimizes Flash device  
energy consumption. The device automatically enables  
this mode when addresses remain stable for t  
+ 50  
ACC  
ns. The automatic sleep mode is independent of the  
CE#, WE#, and OE# control signals. Standard address  
access timings provide new data when addresses are  
changed. While in sleep mode, output data is latched  
and always available to the system. I  
page 25 represents the automatic sleep mode current  
specification.  
in Table 7 on  
After the system writes the autoselect command  
sequence, the device enters the autoselect mode. The  
system can then read autoselect codes from the  
internal register (which is separate from the memory  
array) on DQ7–DQ0. Standard read cycle timings apply  
in this mode. Refer to the Autoselect Mode‚ on page 12  
and Autoselect Command Sequence‚ on page 15 sec-  
tions for more information.  
CC4  
RESET#: Hardware Reset Pin  
The RESET# pin provides a hardware method of reset-  
ting the device to reading array data. When the  
RESET# pin is driven low for at least a period of t , the  
RP  
device immediately terminates any operation in  
progress, tristates all output pins, and ignores all  
read/write commands for the duration of the RESET#  
pulse. The device also resets the internal state  
machine to reading array data. The operation that was  
interrupted should be reinitiated once the device is  
ready to accept another command sequence, to  
ensure data integrity.  
I
in the DC Characteristics table represents the  
CC2  
active current specification for the write mode. AC  
Characteristics‚ on page 28 contains timing specifica-  
tion tables and timing diagrams for write operations.  
Program and Erase Operation Status  
During an erase or program operation, the system may  
check the status of the operation by reading the status  
Current is reduced for the duration of the RESET#  
bits on DQ7–DQ0. Standard read cycle timings and I  
CC  
pulse. When RESET# is held at V  
0.2 V, the device  
read specifications apply. Refer to Write Operation  
Status‚ on page 20 for more information, and to “AC  
Characteristics” for timing diagrams.  
SS  
draws CMOS standby current (I  
). If RESET# is held  
CC4  
at V but not within V  
0.2 V, the standby current is  
IL  
SS  
greater.  
Standby Mode  
The RESET# pin may be tied to the system reset cir-  
cuitry. A system reset would thus also reset the Flash  
memory, enabling the system to read the boot-up firm-  
ware from the Flash memory.  
When the system is not reading or writing to the device,  
it can place the device in the standby mode. In this  
mode, current consumption is greatly reduced, and the  
outputs are placed in the high impedance state, inde-  
pendent of the OE# input.  
If RESET# is asserted during a program or erase oper-  
ation, the RY/BY# pin remains a “0” (busy) until the  
internal reset operation is complete, which requires a  
The device enters the CMOS standby mode when the  
CE# and RESET# pins are both held at V ± 0.2 V.  
(Note that this is a more restricted voltage range than  
time of t  
(during Embedded Algorithms). The  
CC  
READY  
system can thus monitor RY/BY# to determine whether  
the reset operation is complete. If RESET# is asserted  
when a program or erase operation is not executing  
(RY/BY# pin is “1”), the reset operation is completed  
V .) If CE# and RESET# are held at V , but not within  
IH  
IH  
V
± 0.2 V, the device will be in the standby mode, but  
CC  
the standby current will be greater. The device requires  
standard access time (t ) for read access when the  
within a time of t  
(not during Embedded Algo-  
CE  
READY  
device is in either of these standby modes, before it is  
ready to read data.  
rithms). The system can read data t  
after the  
RH  
RESET# pin returns to V .  
IH  
January 23, 2007 27546A6  
Am29SL800D  
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