D A T A S H E E T
tion needed to execute the command. The contents of
DEVICE BUS OPERATIONS
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. Table 1 lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
Table 1. Am29SL800D Device Bus Operations
DQ8–DQ15
BYTE#
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
= VIH
Operation
CE#
L
OE# WE# RESET#
= VIL
Read
Write
L
H
L
H
H
AIN
AIN
DOUT
DIN
DOUT
DIN
DQ8–DQ14 = High-Z,
DQ15 = A-1
L
H
VCC
0.2 V
±
VCC ±
0.2 V
Standby
X
X
X
High-Z
High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
Sector Address, A6 =
L, A1 = H,
Sector Protect (Note)
L
H
L
VID
DIN
X
X
A0 = L
Sector Address, A6 =
H, A1 = H,
Sector Unprotect (Note)
L
H
X
L
VID
VID
DIN
DIN
X
X
A0 = L
Temporary Sector Unprotect
X
X
AIN
DIN
High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment.
ensures that no spurious alteration of the memory
Word/Byte Configuration
content occurs during the power transition. No
The BYTE# pin controls whether the device data I/O
command is necessary in this mode to obtain array
pins DQ15–DQ0 operate in the byte or word configura-
data. Standard microprocessor read cycles that assert
tion. If the BYTE# pin is set at logic ‘1’, the device is in
valid addresses on the device address inputs produce
word configuration, DQ15–DQ0 are active and con-
valid data on the device data outputs. The device
trolled by CE# and OE#.
remains enabled for read access until the command
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
register contents are altered.
See Reading Array Data‚ on page 14 for more informa-
tion. Refer to the AC Read Operations table for timing
specifications and to Figure 13, on page 28 for the
timing diagram. I
in the DC Characteristics table
CC1
represents the active current specification for reading
array data.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V . CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
IL
should remain at V . The BYTE# pin determines
IH
whether the device outputs array data in words or
bytes.
CE# to V , and OE# to V .
IL
IH
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
8
Am29SL800D
27546A6 January 23, 2007
AMD [ AMD ]
