D A T A S H E E T
AC CHARACTERISTICS
Table 10. Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
-90
-100
-120
-150
Unit
90
(Note 3)
tAVAV
tRC
Read Cycle Time (Note 1)
Address to Output Delay
Chip Enable to Output Delay
Min
Max
Max
100
120
150
ns
CE# = VIL
OE# = VIL
90
(Note 3)
tAVQV
tACC
100
120
150
ns
ns
90
(Note 3)
tELQV
tCE
OE# = VIL
100
35
120
50
150
65
tGLQV
tEHQZ
tGHQZ
tOE
tDF
tDF
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Max
Max
Max
Min
30
ns
ns
ns
ns
16
16
0
Read
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
30
0
ns
ns
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
tAXQX
tOH
Notes:
1. Not 100% tested.
2. See Figure 11, on page 27 and Table 8 on page 27 for test specifications
3. VCC min. = 1.7V
.
t
RC
Addresses Stable
Addresses
CE#
t
ACC
t
D
t
OE
OE#
t
OEH
WE#
t
CE
t
O
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
28
Am29SL800D
27546A6 January 23, 2007
AMD [ AMD ]
