D A T A S H E E T
TEST CONDITIONS
Table 8. Test Specifications
-90,
-120,
Test Condition
-100
-150
Unit
Output Load
1 TTL gate
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
Input Pulse Levels
5
0.0–2.0
ns
V
C
L
Input timing measurement
reference levels
1.0
1.0
V
V
Output timing measurement
reference levels
Figure 11. Test Setup
Table 9. Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
2.0 V
0.0 V
1.0 V
1.0 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
January 23, 2007 27546A6
Am29SL800D
27
AMD [ AMD ]
