AMD
using the Sync symbol to define byte boundaries. If the byte boundaries must be
re-aligned (on power-up or re-acquisition of signal), the logic will ensure that the CLK is
stretched (never shortened) upon re-sync to the new byte alignment. Due to this
behavior, the CLK output from the Receiver is not suitable as a direct frequency
reference for another TAXI Transmitter or Receiver. CLK is intended to be used by the
host system as a clock synchronous with the received data.
Fig u re 4 -2
Ca s c a d e d Re c e ive r Clo c k Co n n e c t io n s
From Serial Media
SERIN– SERIN+
SERIN– SERIN+
SERIN– SERIN+
RX1
RX2
RX3
DMS
DMS
IGM
DMS
IGM
V
CC
Am7969
(Primary Receiver)
Am7969
Am7969
CNB
IGM
CLK X2 X1
CNB
CNB
N/C
X2 X1
X2 X1
12.5 MHz
Crystal
OSC
12330E-6
4 .2 .1 Ca s c a d e Mo d e Re c e ive rs (Am 7 9 6 9 -1 2 5 On ly)
When using an on-board TTL clock source, Receivers which are in Cascade mode
should have their X1 pin tied to the Crystal Oscillator and their X2 pin grounded.
Figure 4-2 shows a typical cascaded Receiver clock connection. The frequency source
for the Local mode Receiver should be either a crystal oscillator (as shown) or another
external TTL source. It should not be the CLK output of another Receiver. As discussed
above, the CLK output from the Receiver is not suitable as a frequency source for other
TAXI Receivers.
5 .0 INTERFACING WITH THE S ERIAL MEDIA
The Am7968/Am7969 TAXlchip set is capable of providing a high speed point-to-point
serial link over fiber-optic, coaxial, or twisted pair media. The choice of the appropriate
medium depends primarily on line length and data rate. This chapter discusses the
issues involved in media choice and the requirements for driving different types of
media.
Any TAXIchip set to media interface design must first take into account the electrical
properties of the TAXI Transmitter and TAXI Receiver. The Transmitter serial output
drivers are open emitter, emitter followers which generate pseudo-ECL (PECL) levels
when terminated by pull-down resistors to a voltage more negative than VOL. PECL is
ECL referenced to the +5 V supply, so that VOH = (5–0.8) and VOL = (5–1.8) volts. A safe
termination voltage which guarantees meeting VOL is 3 V or less. The Receiver input is a
long-tailed pair which will switch on 50 mV differential input voltage, with a large
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TAXIchip Integrated Circuits Technical Manual
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