AMD
BLOCK DIAGRAM (continued)
Am7969
(X1)
(X2)
Oscillator
and
Clock Gen.
Serial In+ (SERIN+)
Serial In– (SERIN–)
Media
Interface
Shifter
PLL Clock
Generator
Decoder Latch
(DMS) Data Mode Select
Data Decoder
Output Latch
(CNB) Catch Next Byte
(IGM) I-Got-Mine
Byte Sync
Logic
(CLK) Clock
N
M
(DSTRB) Data Strobe
(VLTN)
Violation
Data Command
(CSTRB) Command Strobe
07370F-2
Note:
N can be 8, 9, or 10 bits Total of N + M = 12
CONNECTION DIAGRAMS
Top View
Am7968
DIPs
LCC/PLCC
1
2
3
4
28
27
26
25
ACK
STRB
DI5
DI4
SEROUT+
SEROUT–
VCC2 (ECL)
DI3
DI2
4
3
2
1
26
28 27
5
6
24
23
DI1
5
6
25
24
V
CC2 (ECL)
DI2
DI1
DI0
V
CC1 (TTL)
V
CC1 (TTL)
7
8
22
21
VCC3 (CML)
RESET
DMS
GND1 (TTL)
GND2 (CML)
X1
7
V
CC3 (TTL)
23 DI0
8
RESET
22
GND1 (TTL)
9
20
19
18
17
16
15
9
21 GND2 (CML)
DMS
TLS
X2
TLS
10
11
12
13
14
10
20
19
X1
X2
TSERIN
CI0
CLK
DI6
11
TSERIN
17 18
12 13 14 15 16
CI1
DI7
07370F-4
DI9/CI2
DI8/CI3
07370F-3
Note:
Pin 1 is marked for orientation.
2
Am7968/Am7969
AMD [ AMD ]
