FINAL
Advanced
Micro
Am7968/Am7969
TAXIchipTM Integrated Circuits
Devices
(Transparent Asynchronous Xmitter-Receiver Interface)
DISTINCTIVE CHARACTERISTICS
■ Parallel TTL bus interface
■ Easy interface with fiber optic data links
■ 32–140 Mbps (4–17.5 Mbyte/s) data
— Eight Data and four Command Pins
— or nine Data and three Command Pins
— or ten Data and two Command Pins
■ Transparent synchronous serial link
— +5 V ECL Serial I/O
throughput
■ Asynchronous input using STRB/ACK
■ Automatic MUX/DEMUX of Data and Command
■ Complete on-chip PLL, Crystal Oscillator
■ Single +5 V supply operation
— AC or DC coupled
■ 28-pin PLCC or DIP or LCC
— NRZI 4B/5B, 5B/6B encoding/decoding
■ Drive coaxial cable or twisted pair directly
GENERAL DESCRIPTION
The Am7968 TAXIchip Transmitter and Am7969
TAXIchip Receiver Chipset is a general-purpose inter-
face for very high-speed (4–17.5 Mbyte/s, 40–175
Mbaud serially) point-to-point communications over co-
axial or fiber-optic media. The TAXIchip set emulates a
pseudo-parallel register. They load data into one side
and output it on the other, except in this case, the “other”
side is separated by a long serial link.
The speed of a TAXIchip system is adjustable over a
range of frequencies, with parallel bus transfer rates of
4 Mbyte/s at the low end, and up to 17.5 Mbyte/s at the
high end. The flexible bus interface scheme of the
TAXIchip set accepts bytes that are either 8, 9, or
10 bits wide. Byte transfers can be Data or Command
signaling.
BLOCK DIAGRAM
Am7968
Data Command
N
M
Strobe &
Acknowledge
Strobe (STRB)
Acknowledge (ACK
Input Latch
X1
Oscillator
and
Encoder Latch
Clock Gen.
X2
Clock (CLK)
Data Encoder
Shifter
Data Mode Select (DMS)
(SEROUT+) Serial Out +
(SEROUT–) Serial Out –
Media
Interface
Test Serial In
Serial Interface
(TSERIN)
Test/Local Select (TLS)
07370F-1
Note:
N can be 8, 9, or 10 bits; total of N + M = 12.
Publication# 07370 Rev. F Amendment/0
Issue Date: April 1994
AMD [ AMD ]
