AMD
15. Jitter on X1input must be less than ±0.2 ns to ensure that automatic test equipment can properly measure device
switching characteristics. The X1 input frequency will determine the byte rate reference for the receiver byte clock.
16. This specification is the sum of Data Dependent Jitter, Duty Cycle Distortion, and Random Jitter.
18. ACK delay is determined by t13 when the input latch is empty or by t15 when the latch is full (Busy mode). Also note that ACK
will not rise if STRB does not remain HIGH until ACK rises.
19. If t47A (CNBØto CLK≠setup) is violated, then output data will occur one byte time later.
20. All timing references are made with respect to +1.5 V for TTL–level signals or to the 50% point between VOH and VOL for
ECL signals. ECL input rise and fall times must be 2 ns ±0.2 ns between 20% and 80% points. TTL input rise and fall times
must be 2 ns between 1 V and 2 V.
21. Device thresholds on the SERIN (+/–) pin(s) are verified during production test by ensuring that the input threshold is less
than VIHS (min) and greater than VILS (max). The figure below shows the acceptable range (shaded area) for the transition
voltage.
VCC
VCC = 0.88 V
VCC = 1.165 V
Input threshold
transition voltage
VCC = 1.475 V
VCC = 1.81 V
22. Switching Characteristics are tested during 8-bit local mode operation.
23. The limit for this parameter cannot be derived from t37 and t42.
24. This specification does not apply during reacquisition when CLK stretch can occur.
✝ This parameter is guaranteed but is not included in production tests.
*
Notes listed correspond to the respective references made in the DC Characteristics and the Switching Characteristics
tables.
Am7968/Am7969
39
AMD [ AMD ]
