AMD
Notes:*
1. For conditions shown as Min or Max use the appropriate value specified under operating range.
2. The clock fall to serial output delay is typically 3 bit times.
4. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
5. If the CNB↑ to CLK↑ setup time is violated, IGM will stay LOW.
6. Voltage applied to either SERIN± pins must not be above VCC nor below +2.5 V to assure proper operation.
7. t4 guarantees that data is latched. ACK (t11) timing may not be valid.
8. If t11 is not met, ACK response and timing are not guaranteed, but data will still be latched on STRB↑ (see t4).
9. Measured with device in Test mode while monitoring output logic states.
10. For the TAXI Transmitter, “n” is determined by the following table:
DMS
GND
TLS
“n”
8 Bit
Test Mode 2
OPEN
n = 1;
8 Bit
GND/VCC
OPEN
n = 10;
n = 1;
Local/Test Mode 1
9 Bit
Test Mode 2
VCC
9 Bit
GND/VCC
OPEN
n = 11;
Local/Test Mode 1
10 Bit
Test Mode 2
Open
or
n = 1;
1
2
10 Bit
Local/Test Mode 1
GND/VCC
VCC
n = 12;
11. t6 (Internal Byte Boundary to CLK↓) is created by the variation of internal STRB propagation delays relative to internal byte
boundaries over temperatures and VCC. The internal byte boundary determines the byte in which data will come out
(SEROUT±). If STRB occurs before the byte boundary, then the data will be sent out two bytes later. If STRB occurs after the
byte boundary, then the output data will be delayed by one additional byte.
12. X1 Pulse Width is measured at a point where CLK output equals t2 or t3.
13. For the TAXI Transmitter, ‘Data’ is either DI0 – DI7, DI8/CI3, DI9/CI2, CI0 – CI1. For the TAXI Receiver, ‘STRB’ is either
CSTRB or DSTRB and ‘Data’ is either DO0 – DO7, DO8/CO3, DO9/CO2, CO0 – CO1.
14. For the TAXI Receiver, ‘n’ is determined by the state of the DMS and SERIN–
inputs. When SERIN– is held below VTHT max or left open, n=1. When SERIN– is held above 0.25 V and when:
DMS
GND
SERIN–
“n”
8 Bit
Test Mode
< VTHTMAX or OPEN
n = 1;
8 Bit
Local Mode
> 2.5 V
n = 10;
n = 1;
9 Bit
Test Mode
< VTHTMAX or OPEN
> 2.5 V
VCC
9 Bit
Local Mode
n = 11;
10 Bit
Open
or
< VTHTMAX or OPEN
> 2.5 V
n = 1;
Test Mode
1
10 Bit
Local Mode
VCC
n = 12;
2
38
Am7968/Am7969
AMD [ AMD ]
