AMD
SWITCHING CHARACTERISTICS (Note 20)
Am7968-125 TAXIchip Transmitter (Notes 10, 13, 22)
Parameter
No.
Symbol
Parameter Description
Test Conditions
Min
Max
Units
Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK
1
2
3
4
5
6
tP
CLK Period
8n
30
30
15
15
25n
ns
ns
ns
ns
ns
ns
tPW
tPW
tPW
tPW
tBB
CLK Pulse Width HIGH
CLK Pulse Width LOW
STRB Pulse Width HIGH (Note 7)
STRB Pulse Width LOW
–9t1
Internal Byte Boundary to CLK↓
(Note 11)
20
+9
8n
9
tS
Data–STRB Setup Time
Data–STRB Hold Time
ACK↑ to STRB↓ Hold (Note 8)
ACK↓ to STRB↑ Hold
STRB↑ to ACK↑ (Note 18)
STRB↓ to ACK↓
5
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
tH
15
0
tH
TTL Output Load
TTL Output Load
TTL Output Load
TTL Output Load
TTL Output Load
tH
0
tPD
tPD
tPD
40
23
3t1
CLK↓ to ACK↑ (Note 18)
+ 33
n
Serial Interface Signals: SEROUT+, SEROUT– (Note 2)
✝
22
23
24
26
tSK
SEROUT± Skew
ECL Output Load
ECL Output Load
ECL Output Load
ECL Output Load
–200
.45
+200
ps
ns
ns
ns
✝
tR
SEROUT± Output Rise Time
SEROUT± Output Fall Time
SEROUT ± Pulse Width LOW
2
2
✝
tF
.45
✝
✝
tPW
t1
t1
n
– 5%
– 5%
+ 5%
+ 5%
n
t1
n
t1
n
27
tPW
SEROUT ± Pulse Width HIGH
ECL Output Load
ns
Miscellaneous Signals: X1 (Note 15)
29
30
32
33
tPW
tPW
tPD
tPD
X1 Pulse Width HIGH (Note 12)
X1 Pulse Width LOW (Note 12)
X1 ↑ to CLK↑
TTL Output Load on CLK
TTL Output Load on CLK
TTL Load
35
35
ns
ns
ns
ns
32
32
X1 ↓ to CLK↓
TTL Load
24
Am7968/Am7969-125
AMD [ AMD ]
