Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
as viewed by the Add-On. The flexibility of this
arrangement allows a number of user-defined soft-
ware protocols to be built. For example, data, software
assigned commands, and command parameters can
be exchanged between the PCI and Add-On buses
using either the mailboxes or FIFOs with or without
handshaking interrupts. The register structure is very
similar to that of the PCI operation register set. The
major difference between the PCI bus and Add-On
bus register complement are the absence of bus mas-
ter control registers (4) on the Add-On side and the
addition of two “pass-through” registers. Table 1 lists
the Add-On interface registers.
ADD-ON BUS OPERATION REGISTERS
The Add-On bus interface provides access to 18
DWORDs (72 bytes) of data, control and status infor-
mation. All of these locations are accessed by
asserting the Add-On bus chip select pin (SELECT#)
in conjunction with either the read or write control
strobes (signal pin RD# or WR#). Access to the FIFO
can also be achieved through use of the dedicated
pins, RDFIFO# and WRFIFO#. The dedicated pins for
control of the FIFO are provided to optionally imple-
ment Direct Memory Access (DMA) on the Add-On
bus, or to connect with an external FIFO.
This register group represents the primary method for
communication between the Add-On and PCI buses
Table 34. Operation Registers — Add-On Interface
Address
00h
Abbreviation
AIMB1
Register Name
Add-On Incoming Mailbox Register #1
04h
AIMB2
Add-On Incoming Mailbox Register #2
Add-On Incoming Mailbox Register #3
Add-On Incoming Mailbox Register #4
Add-On Outgoing Mailbox Register #1
Add-On Outgoing Mailbox Register #2
Add-On Outgoing Mailbox Register #3
Add-On Outgoing Mailbox Register #4
Add-On FIFO port
08h
AIMB3
0Ch
10h
AIMB4
AOMB1
AOMB2
AOMB3
AOMB4
AFIFO
14h
18h
1Ch
20h
MWAR1
APTA
24h
Bus Master Write Address Register
28h
2Ch
30h
Add-On Pass-Through Address
Add-On Pass-Through Data
APTD
MRAR1
AMBEF
AINT
Bus Master Read Address Register
34h
38h
3Ch
58h
Add-On Mailbox Empty/Full Status
Add-On Interrupt control
AGCSTS
Add-On General Control and Status Register
Bus Master Write Transfer Count
MWTC1
MRTC1
5Ch
Bus Master Read Transfer Count
1. See Add-On Initiated Bus Mastering.
76
DS1527
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
