Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
The latency timer register has meaning only when this
controller is used as a bus master and pertains to the
number of PCI bus clocks that this master will be guar-
anteed. The nonzero value for this register is internally
decremented after this device has been granted the
bus and has begun to assert FRAME#. Prior to this
latency timer count reaching zero, this device can
ignore the removal of the bus grant and may continue
the use of the bus for data transfers.
LATENCY TIMER REGISTER (LAT)
Latency Timer
Register Name
Address Offset
Power-up value
Boot-load
0Dh
00h
External nvRAM offset 04Dh
Read/Write, bits 7:3; Read Only bits
2:0
Attribute
Size
8 bits
Figure 15. Latency Timer Register
7
6
5
4
3
2
0
1
0
0
0
Bit
X
X
X
X
X
Value
Latency Timer value (R/W)
# of clocks x 8
46
DS1527
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
