Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
Figure 82. Single Cycle Pass-Thru Read with PTADR#
012345
BPCLK
6
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1
0h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
2Ch
0h
WR#
DQ[31:0]
PTRDY#
PTADR#
PT ADDR
PT DATA
Data stored in Pass-Thru
data register
PCI Read cycle completed
Figure 83. Pass-Thru Burst Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
BPCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1
0h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
RD#
2Ch
0h
PT ADDRDATA1 DATA2 DATA3
XXXX DATA4
XXXX
DATA5 DATA6
XXXX
DQ[31:0]
PTRDY#
PTADR#
s
Valid PCI data on DQ bu
PCI Bu
rst Write completed
Figure 5 also shows a 5 data phase Pass-Thru burst
write, but the Add-On logic uses PTRDY# to control
the rate at which data is transferred. In many applica-
tions, Add-On logic is not fast enough to accept data at
every BPCLK rising edge (every 30 ns in a 33 MHz
PCI system). In this example, the Add-On interface
accepts data every other clock. In the example, RD# is
asserted during the entire Add-On burst, but it can be
deasserted when PTRDY# is deasserted, the S5935
functions the same under both conditions.
158
DS1527
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
