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S5935_07 参数 Datasheet PDF下载

S5935_07图片预览
型号: S5935_07
PDF下载: 下载PDF文件 查看货源
内容描述: PCI产品 [PCI Product]
分类和应用: PC
文件页数/大小: 204 页 / 3916 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.02 – June 27, 2006  
S5935 – PCI Product  
Data Book  
The Add-On PTADR# input directly accesses the  
Pass-Thru Address Register and drives the contents  
onto the data bus (no BPCLK rising edge is required).  
The byte enables, address, and SELECT# inputs are  
ignored when PTADR# is asserted. RD# and WR#  
must not be asserted when PTADR# is asserted.  
The PCI bus cycle address is stored in the S5935 Pass-Thru Address Register.  
Clock 0:  
Clock 1:  
The PCI address is recognized as an access to Pass-Thru region 1. PCI data is stored in the S5935 Pass-Thru  
Data Register. PTATN# is asserted to indicate a Pass-Thru access is occurring.  
Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid  
when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2.  
Clock 2:  
PTBURST#  
Deasserted. The access has a single data phase.  
PTNUM[1:0] 01. Indicates the PCI access is to Pass-Thru region 1.  
PTWR  
Asserted. The Pass-Thru access is a write.  
0h. Indicate the Pass-Thru access is 32-bits.  
PTBE[3:0]#  
The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and  
SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3.  
SELECT#, byte enable, and the address inputs remain valid to read the Pass-Thru Data Register at offset 2Ch.  
RD# is asserted to drive data register contents onto the DQ bus.  
Clock 3:  
Clock 4:  
Clock 5:  
If PTRDY# is asserted at the rising edge of clock 4, PTATN# is immediately deasserted and the Pass-Thru  
access is completed at clock 5.  
If Add-On logic requires more time to read the Pass-Thru Data Register (slower memory or peripherals),  
PTRDY# can be delayed, extending the cycle. PTRDY# asserted at the rising edge of clock 5 causes PTATN# to  
be immediately deasserted.  
PTATN# and PTBURST# deasserted at the rising edge of clock 6 indicates the Pass-Thru access is complete.  
The S5935 can accept new Pass-Thru accesses from the PCI bus at clock 7.  
Clock 6:  
AMCC Confidential and Proprietary  
DS1527  
155  
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