Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
Some applications hold the RDFIFO# and WRFIFO#
inputs active for a synchronous interface. In 16-bit
mode, designs must avoid writing to a full FIFO. The
data for the write is lost, but the internal mechanism to
direct the 16-bit external data bus to the upper 16-bits
of the FIFO register is triggered. This creates a situa-
tion where the FIFO is out of step. The next 16-bit
FIFO write is directed to the upper 16-bits of the FIFO,
and the FIFO advances incorrectly. The WRFULL out-
put should be used to gate the WRFIFO# input to
avoid this situation. A similar problem can occur if
Add-On logic attempts to read an empty FIFO in 16-bit
mode. RDEMPTY should be used to gate the
RDFIFO# input to avoid problems with the FIFO get-
ting out of step. In 32-bit mode (MODE = low), these
situations do not occur.
Bits 6 and 5 in location 45h enable FIFO register
accesses using the RDFIFO#, WRFIFO#, RD# and
WR# inputs synchronous to BPCLK. For synchronous
operation, RDFIFO#, WRFIFO#, RD# and WR# oper-
ate as enables, using BPCLK to clock data.
Location 45h Configuration Bits
Bit 7 Bus Master Register Access
0
Address and transfer count registers only accessi-
ble from the Add-On interface
1
Address and transfer count registers only accessi-
ble from the PCI interface (default)
Bit 6 RDFIFO#, RD# Operation
If FIFO accesses are done without the direct access
signals with MODE configured for 16-bits (using ADR,
SELECT#, etc.), external hardware must toggle ADR1
between consecutive 16-bit bus cycles. The FIFO
advance condition must be set to correspond to the
order the application accesses the upper and lower
words in the FIFO register.
0
1
Enable - RDFIFO# and RD# functions.
Not allowed. Must be 0.
Bit 5 WRFIFO#, WR# Operation
0
1
Enable - WRFIFO# and WR# functions.
Not allowed. Must be 0.
CONFIGURATION
Bit 0 Target Latency Timer Enable
The FIFO configuration takes place during initialization
and during operation. During initialization, the bus
master register access rights are defined. During oper-
ation, FIFO advance conditions, endian conversion,
and bus mastering capabilities are defined. The follow-
ing section describes the bits and registers which are
involved with controlling and monitoring FIFO
operation.
0
1
Disable PCI Latency Timer Time Out - Will not dis-
connect with retry if cannot issue TRDY in speci-
fied time
Enable PCI Latency Timer Time Out - Will be PCI
2.1 compliant
FIFO Status and Control Bits
FIFO Setup During Initialization
The FIFO status can be monitored and the FIFO oper-
ation controlled from the PCI Operation Registers and/
or the Add-On Operation Registers. The FIFO register
resides at offset 20h in the PCI and Add-On Operation
Registers.
Location 45h in an external non-volatile memory may
be used to configure the S5935 FIFO during initializa-
tion. If no external non-volatile memory is used, FIFO
operation is disabled.
The value of bit 7 in location 45h determines if the
address and transfer count registers used in bus mas-
tering are accessible from the PCI bus or from the
Add-On bus. Once the configuration information is
downloaded from non-volatile memory after reset, the
bus mastering initialization method can not be
changed. Access to the bus master address and trans-
fer count registers cannot be alternated between the
PCI bus and the Add-On interface during operation.
The Bus Master Control/Status (MCSR) PCI Operation
register allows a PCI host to monitor FIFO activity and
control FIFO operation. Reset controls allow the PCI to
Add-On FIFO and Add-On to PCI FIFO flags to be
reset (individually). Status bits indicate if the PCI to
Add-On FIFO is empty, has four or more open spaces,
or is full. Status bits also indicate if the Add-On to PCI
FIFO is empty, has four or more full locations or is full.
Finally, FIFO PCI bus mastering is monitored/con-
trolled though this register.
146
DS1527
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