Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
Master-Initiated Termination
Normal Cycle Completion
Occasionally, a PCI transfer must be terminated by the
initiator. Typically, the initiator terminates a transfer
upon the successful completion of the transfer. Some-
times, the initiator’s bus mastership is relinquished by
the bus arbiter (GNT# is removed), often because
another device requires bus ownership. This is called
initiator preemption and is discussed in later Sections.
When the S5935 is an initiator and does not observe a
DEVSEL# response to its assertion of FRAME#, it ter-
minates the cycle (master abort).
A successful data transfer occurs when both the initia-
tor and target assert their respective ready signals,
IRDY# and TRDY#. The last data phase is indicated
by the initiator when FRAME# is deasserted during a
data transfer. A normal cycle completion occurred if
the target does not assert STOP#. Figure 6 shows the
signal relationships defining a normal transfer
completion.
Figure 50. Single Data Phase PCI Bus Write of S5935 Registers (S5935 as Target)
3
2
45
6
1
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
(I)
(I)
IF BURST
ATTEMPT
DATA 1
DATA 2
ADDRESS
BYTE EN 1
BYTE EN 2
BUS COMMAND
(I)
(I)
TRDY#
(T)
(T)
(T)
DEVSEL#
STOP#
NO
DATA
TRANSFERRED
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
DATA
TRANSFER #1
Figure 51. Master-Initiated, Normal Completion (S5935 as either Target or Initiator)
3
2
1
PCI CLOCK
FRAME #
IRDY#
(I)
(I)
TRDY#
(T)
(T)
(T)
DEVSEL#
STOP#
NORMAL
COMPLETION
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
PCI BUS INTERFACE S5935
AMCC Confidential and Proprietary
DS1527
105
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
