Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
Read accesses from the S5935 operation registers
(S5935 as a target) are shown in Figure 2. The S5935
conditionally asserts STOP# in clock period 3 if the ini-
tiator keeps FRAME# asserted during clock period 2
with IRDY# asserted (indicating a burst is being
attempted). Wait states may be added by the initiator
by not asserting the signal IRDY# during clock 3 and
beyond. If FRAME# remains asserted, but IRDY# is
not asserted, the initiator is just adding wait states, not
necessarily attempting a burst.
target disconnect and occurs when a read attempt is
made to an empty S5935 FIFO. The assertion of
STOP# without the assertion of TRDY# indicates that
the initiator should retry the operation later.
When burst read transfers are attempted to the S5935
operation registers, STOP# is asserted during the first
data transfer to indicate to the initiator that no further
transfers (data phases) are possible. This is a target
initiated termination where the target disconnects after
the first data transfer. Figure 3 shows the signal rela-
tionships during a burst read attempt to the S5935
operation registers.
There is only one condition where accesses to S5935
operation registers do not return TRDY# but do assert
STOP#. This is called a target-initiated termination or
Figure 47. Single Data Phase PCI Bus Read of S5935 Registers (S5935 as Target)
2
3
45
1
(I)
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
(T)
(I)
ADDRESS
DATA
(I)
BUS COMMAND
BYTE ENABLES
(I)
(T)
TRDY#
DEVSEL#
STOP#
(T)
(T)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
Figure 48. Burst PCI Bus Read Attempt to S5935 Registers (S5935 as Target)
3
2
1
45
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
(I)
(T)
(I)
DATA
ADDRESS
BE (2)
BUS COMMAND
BYTE ENABLES (1)
(I)
(I)
TRDY#
(T)
(T)
(T)
DEVSEL#
STOP#
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
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DS1527
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
