S5935
ARCHITECTURAL OVERVIEW
The S5935 is an off-the-shelf, low-cost, standard prod-
uct, which is PCI 2.1 compliant. And, since AMCC is a
member of the PCI Special Interest Group, the S5935
has been tested on various manufacturer’s PCI
motherboards, chip sets, PCI BIOSs and operating
systems. This removes the burden of compliance and
compatibility testing from the designer and thus signifi-
cantly reduces development time. Utilizing the S5935
allows the designer to focus on the actual application,
not debugging the PCI interface.
Figure 2.
PCLK
BPCLK
IRQ#
SYSRST#
S5935
Add-On Bus
Control
INTA#
RST#
Add-On
Data Bus
AD[31:0]
DQ[31:0]
C/BE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
RD#
S5933 Register
Access
REQ#
GNT#
PCI
Local
Bus
FRAME#
DEVSEL#
IRDY#
WR#
The S5935 allows special direct data accessing be-
tween the PCI bus and the user application through
implementation of four definable Pass-Thru data chan-
nels. Each data channel is implemented by defining a
Host memory segment size and 8/16/32-bit user bus
width. The addition of two 32 byte FIFOs, also used in
S5935 Bus Mastering applications, provides further
versatilitytodatatransfercapabilities. FIFODMAtrans-
fers are supported using Address and Transfer Count
Registers. Four32-bitMailboxRegisterscoupledwitha
Status Register and extensive interrupt capabilities
provide flexible user command or message transfers
between the two buses. In addition, the S5935 also
allows use of an external serial, or byte-wide non-
volatile memory to perform any pre-boot initialization
requirementsandtoprovidecustomexpansionBIOSor
POST code capability.
PTATN#
PTBURST#
PTNUM[1:0]#
PTBE[3:0]#
PTADR#
TRDY#
IDSEL#
Pass-Thru
Control/Access
STOP#
LOCK#
PTWR
PTRDY#
PAR
PERR#
SERR#
RDFIFO#
WRFIFO#
RDEMPTY
WRFULL
Direct FIFO
Access
MODE
SNV
S5935
Control
EA[15:0]
EQ[7:0]
Byte Wide
Config/BIOS Opt.
Serial Bus
Config/BIOS Opt.
EWR#/SDA
ERD#/SCL
S5935 Register Architecture
S5935 ARCHITECTURE
Control and configuration of the Add-On Local bus, and
the S5935 itself, is performed through three primary
groups of registers. These groups consist of PCI Con-
figuration Registers, PCI Operation Registers and Add-
On Operation Registers. These registers are user
configurablethrougheithertheirassociatedbusorfrom
an external non-volatile memory device. This section
will provide a brief overview of each of these register
groups and the optional non-volatile interface.
The block diagram in Figure 1 above shows the major
functional elements within the S5935. The S5935 pro-
vides three physical bus interfaces: the PCI Local bus,
the user local bus referred to as the Add-On Local bus
and the optional serial and byte-wide non-volatile
memory buses. Data movement between buses can
take place through mailbox registers or the FIFO data
channel, or a user can define and enable one or more
ofthefourPass-Thrudatachannels. S5935BusMaster
orDMAdatatransferstoandfromthePCILocalbusare
performed through the FIFO data channel under either
Host or Add-On software control or Add-On hardware
control using dedicated S5935 signal pins.
PCI Configuration Registers
All PCI compliant devices are required to provide a
group of Configuration Registers for the host system.
These registers are polled during power up initialization
and contain specific device and add-in card product
information including Vendor ID, Device ID, Revision
and the amount of memory required for product opera-
tion. The S5935 can either load these registers with
default values or initialize them from an external non-
volatile memory area called ‘Configuration Space’. The
S5935 can accommodate a total of 256 bytes of exter-
nal memory for this purpose. The first 64 bytes is
reserved for user defined configuration data which is
loaded into the PCI Configuration Registers during
power-up initialization. The remaining 192 bytes may
be used to implement an Expansion BIOS or contain
add-in card POST code. Table 1 shows all the S5935
PCI Configuration Registers.
The S5935 signal pins are shown in Figure 2. The PCI
Local Bus signals are detailed on the left side; Add-On
Local Bus signal are detailed on the right side. All
additional S5935 device control signals are shown on
the lower right side.
The S5935 supports a two wire serial nvRAM bus and
a byte-wide EPROM/FLASH bus. This allows the de-
signer to customize the S5935 configuration by loading
setup information on system power-up.
1-2
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
