Target Disconnects ..................................................................................................................
Target Requested Retries ........................................................................................................
Target Aborts ...........................................................................................................................
PCI Bus Mastership ...........................................................................................................................
Bus Mastership Latency Components .....................................................................................
Bus Arbitration .........................................................................................................................
Bus Acquisition ........................................................................................................................
Target Latency .........................................................................................................................
Target Locking .........................................................................................................................
PCI Bus Interrupts ...............................................................................................................................
PCI Bus Parity Errors ..........................................................................................................................
7-92
7-93
7-93
7-95
7-95
7-95
7-96
7-96
7-96
7-98
7-98
Add-On Operation Register Accesses ................................................................................................ 8-99
Add-On Interface Signals ........................................................................................................ 8-99
System Signals ........................................................................................................................ 8-99
Register Access Signals .......................................................................................................... 8-99
Asynchronous Register Accesses ......................................................................................... 8-100
Synchronous FIFO and Pass-Thru Data Register Accesses ................................................. 8-100
nv Memory Accesses Through the Add-On General Control/Status Register ....................... 8-100
Mailbox Bus Interface ....................................................................................................................... 8-100
Mailbox Interrupts .................................................................................................................. 8-103
FIFO Bus Interface ............................................................................................................................ 8-103
FIFO Direct Access Inputs ..................................................................................................... 8-103
FIFO Status Signals .............................................................................................................. 8-103
FIFO Control Signals ............................................................................................................. 8-103
Pass-Thru Bus Interface ................................................................................................................... 8-103
Pass-Thru Status Indicators .................................................................................................. 8-104
Pass-Thru Control Inputs ....................................................................................................... 8-104
Non-Volatile Memory Interface .......................................................................................................... 8-104
Non-Volatile Memory Interface Signals ................................................................................. 8-104
Accessing Non-Volatile Memory ............................................................................................ 8-105
nv Memory Device Timing Requirements .............................................................................. 8-107
Functional Description ...................................................................................................................... 9-109
Mailbox Empty/Full Conditions ............................................................................................... 9-110
Mailbox Interrupts ................................................................................................................... 9-110
Add-On Outgoing Mailbox 4, Byte 3 Access ........................................................................... 9-110
Bus Interface ...................................................................................................................................... 9-111
PCI Bus Interface ................................................................................................................... 9-111
Add-On Bus Interface ............................................................................................................. 9-111
8-Bit and 16-Bit Add-On Interfaces ......................................................................................... 9-111
Configuration ...................................................................................................................................... 9-112
Mailbox Status ........................................................................................................................ 9-112
Mailbox Interrupts ................................................................................................................... 9-113
iii
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
