Revision 1.02 – April 12, 2007
S5920 – PCI Product: PCI Configuration Registers
Data Book
The cache line configuration register is used by bus
masters implementing memory write and invalidate
commands. The register defines the cache line size in
double word (64-bit) increments. The S5920 is a target
device not requiring cache. The register is hardwired
to 0.
CACHE LINE SIZE REGISTER (CALN)
Cache Line Size
Register Name:
0Ch
Address Offset:
Power-up value:
Boot-load:
Attribute:
00h, hardwired
not used
Read Only
8 bits
Size:
Figure 13. Cache Line Size Register
7
0
00h
Cache Line Size (RO)
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DS1596
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