Revision 1.02 – April 12, 2007
S5920 – PCI Product
Data Book
Base Class Code 0Bh: Processors ................................................................................................................. 53
Base Class Code 0Ch: Serial Bus Controllers ................................................................................................ 53
CACHE LINE SIZE REGISTER (CALN) ............................................................................................................... 54
Cache Line Size Register ................................................................................................................................ 54
LATENCY TIMER REGISTER (LAT) .................................................................................................................... 55
Latency Timer Register ................................................................................................................................... 55
HEADER TYPE REGISTER (HDR) ....................................................................................................................... 56
Header Type Register ..................................................................................................................................... 56
BUILT-IN SELF-TEST REGISTER (BIST) ............................................................................................................ 57
Built-In Self-Test Register ................................................................................................................................ 57
BASE ADDRESS REGISTER (BADR) ................................................................................................................. 58
Determining Base Address Size ...................................................................................................................... 58
Assigning the Base Address ............................................................................................................................ 58
Base Address Register - Memory .................................................................................................................... 59
Base Address Register - I/O ............................................................................................................................ 60
Base Address Register Response (Memory Assigned) to All-Ones Write Operation ..................................... 61
Read Response (I/O Assigned) to an All-Ones Write Operation to a Base Address Register ........................ 62
SUBSYSTEM VENDOR IDENTIFICATION REGISTER (SVID) ........................................................................... 63
Subsystem Vendor Identification Register ....................................................................................................... 63
SUBSYSTEM ID REGISTER (SID) ....................................................................................................................... 64
Subsystem Identification Register ................................................................................................................... 64
EXPANSION ROM BASE ADDRESS REGISTER (XROM) ................................................................................. 65
Expansion ROM Base Address Register ......................................................................................................... 65
Read Response to Expansion ROM Base Address Register (after all ones written) ...................................... 66
INTERRUPT LINE REGISTER (INTLN) ................................................................................................................ 67
Interrupt Line Register ..................................................................................................................................... 67
INTERRUPT PIN REGISTER (INTPIN) ................................................................................................................ 68
Interrupt Pin Register ....................................................................................................................................... 68
MINIMUM GRANT REGISTER (MINGNT) ............................................................................................................ 69
Minimum Grant Register .................................................................................................................................. 69
MAXIMUM LATENCY REGISTER (MAXLAT) ...................................................................................................... 70
Maximum Latency Register ............................................................................................................................. 70
OPERATION REGISTERS .................................................................................................................................... 71
PCI BUS OPERATION REGISTERS .................................................................................................................... 71
Operation Registers - PCI Bus ........................................................................................................................ 71
OUTGOING MAILBOX REGISTER (OMB) ........................................................................................................... 72
Outgoing Mailbox ............................................................................................................................................. 72
PCI INCOMING MAILBOX REGISTER (IMB) ....................................................................................................... 73
Incoming Mailbox ............................................................................................................................................. 73
PCI MAILBOX EMPTY/FULL STATUS REGISTER (MBEF) ................................................................................ 74
Mailbox Empty/Full Status Register (MBEF) ................................................................................................... 74
Mailbox Empty/Full Status Register ................................................................................................................. 74
PCI INTERRUPT CONTROL/STATUS REGISTER (INTCSR) ............................................................................. 75
Interrupt Control Status Register ..................................................................................................................... 75
Interrupt Control Status Register ..................................................................................................................... 76
PCI RESET CONTROL REGISTER (RCR) ........................................................................................................... 77
AMCC Confidential and Proprietary
DS1596
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
