Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Synchronous RD# FIFO Timing
Table 68. Synchronous RD# FIFO Timing
Functional Operation Range (V = 3.3V ±5%, 0°C to 70°C, 50 pf load on outputs)
CC
Symbol
Parameter
SELECT# Setup to BPCLK Rising Edge
SELECT# Hold from BPCLK Rising Edge
ADR[6:2] Setup to BPCLK Rising Edge
ADR[6:2] Hold from BPCLK Rising Edge
BE[3:0]# Setup to BPCLK Rising Edge
BE[3:0]# Hold from BPCLK Rising Edge
RD# Low to DQ[31:0] Driven
Min
15
0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
t
t
t
t
t
t
t
t
t
t
t
t
-
-
112
112a
116
22
0
-
-
116a
120
120a
125
128
156
157
124
124a
127
17
0
-
-
-
13
8
RD# High to DQ[31:0] Float
-
RDEMPTY Status Valid to BPCLK Rising Edge
FRF Status Valid to BPCLK Rising Edge
RD# Setup to BPCLK Rising Edge
-
15
74
-
-
15
0
RD# Hold from BPCLK Rising Edge
DQ[31:0] Valid from BPCLK Rising Edge
-
-
15
Notes:
1. RD# and SELECT# must both be asserted to drive DQ[31:0] - delay is from the last one asserted.
2. When increasing Setup times, ADR[6:2], BE[3:0]#, SELECT#, and RD# timing relations remain relative to each other as shown.
Figure 103. Synchronous RD# FIFO Timing
BPCLK
t112
t112a
SELECT#
t116
t116a
ADR[6:2]
t120
t120a
BE[3:0]#
t125
DQ[31:0]
t128
t124a
t124
RD#
t156
5ns
RDEMPTY
t157
FRF
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