Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Synchronous RDFIFO# Timing
Table 64. Synchronous RDFIFO# Timing
Functional Operation Range (V = 3.3V ±5%, 0°C to 70°C, 50 pf load on outputs)
CC
Symbol
144
Parameter
RDFIFO# Setup to BPCLK Rising Edge
Min
Max
Units
Notes
t
t
t
t
t
t
t
15
-
ns
RDFIFO# Low Time
8
-
-
ns
ns
ns
ns
ns
ns
145
RDFIFO# Low to DQ[31:0] Driven
13
8
146
RDFIFO# High to DQ[31:0] Float
-
148
DQ[31:0] Valid from BPCLK Rising Edge
PCI to ADD-ON FIFO RDEMPTY Valid from BPCLK Rising Edge
PCI to ADD-ON FIFO FRF Valid from BPCLK Rising Edge
-
15
15
80
149
-
165
-
166
Notes:
1. Valid applies after first access. First access is async with following as sync accesses.
2. State change of RDEMPTY shown below is reference only.
Figure 99. Synchronous RDFIFO# Timing
BPCLK
t149
t144
RDFIFO#
DQ[31:0]
t148
14ns
6ns
8ns
t146
10ns
t165
New Valid
t166
RDEMPTY
FRF
Old Valid
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