Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 107. Pass-Thru Data Register Read Timing
BPCLK
t
t
14
13
ADR[6:2]
BE[3:0]#
Valid 1
Valid 2
t
t
33
17
DQ[31:0]
RD#
Valid Data Out 1
Valid Data Out 2
t
12
t
t
30
29
t
34
SELECT#
PTRDY#
t
11a
t
t
27
26
Figure 108. Pass-Thru Data Register Write Timing
BPCLK
t
t
14
13
ADR[6:2]
BE[3:0]#
Valid 1
Valid 2
t
t
32
31
DQ[31:0]
WR#
Valid Data In 1
Valid Data In 2
t
t
30
29
SELECT#
PTRDY#
t
t
11a
10a
t
26
t
27
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