Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
The S5335 is an off-the-shelf, low-cost, standard prod-
uct, which is PCI 2.1 compliant. And, since AMCC is a
member of the PCI Special Interest Group, the S5335
has been tested on various manufacturer’s PCI moth-
erboards, chip sets, PCI BIOSs and operating
systems. This removes the burden of compliance and
compatibility testing from the designer and thus signifi-
cantly reduces development time. Utilizing the S5335
allows the designer to focus on the actual application,
not debugging the PCI interface.
Figure 2. S5335 Pinout
PCLK
INTA#
RST#
BPCLK
IRQ#
SYSRST#
S5335
Add-On Bus
Control
Add-On
Data Bus
AD[31:0]
DQ[31:0]
C/BE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
RD#
S5933 Register
Access
REQ#
GNT#
PCI
Local
Bus
FRAME#
DEVSEL#
IRDY#
WR#
PTATN#
The S5335 allows special direct data accessing
between the PCI bus and the user application through
implementation of four definable Pass-Thru data chan-
nels. Each data channel is implemented by defining a
Host memory segment size and 8/16/32-bit user bus
width. The addition of two 32 byte FIFOs, also used in
S5335 Bus Mastering applications, provides further
versatility to data transfer capabilities. FIFO DMA
transfers are supported using Address and Transfer
Count Registers. Four 32-bit Mailbox Registers cou-
pled with a Status Register and extensive interrupt
capabilities provide flexible user command or mes-
sage transfers between the two buses. In addition, the
S5335 also allows use of an external serial, or byte-
wide non-volatile memory to perform any pre-boot ini-
tialization requirements and to provide custom
expansion BIOS or POST code capability.
TRDY#
IDSEL#
PTBURST#
PTNUM[1:0]#
PTBE[3:0]#
PTADR#
Pass-Thru
Control/Access
STOP#
LOCK#
PTWR
PTRDY#
PAR
PERR#
SERR#
RDFIFO#
WRFIFO#
RDEMPTY
WRFULL
Direct FIFO
Access
MODE
SNV
S5935
Control
EA[15:0]
EQ[7:0]
Byte Wide
Config/BIOS Opt.
Serial Bus
Config/BIOS Opt.
EWR#/SDA
ERD#/SCL
S5335 Register Architecture
Control and configuration of the Add-On Local bus,
and the S5335 itself, is performed through three pri-
mary groups of registers. These groups consist of PCI
Configuration Registers, PCI Operation Registers and
Add-On Operation Registers. These registers are user
configurable through either their associated bus or
from an external non-volatile memory device. This
section will provide a brief overview of each of these
register groups and the optional non-volatile interface.
S5335 ARCHITECTURE
The block diagram in Figure 2 above shows the major
functional elements within the S5335. The S5335 pro-
vides three physical bus interfaces: the PCI Local bus,
the user local bus referred to as the Add-On Local bus
and the optional serial and byte-wide non-volatile
memory buses. Data movement between buses can
take place through mailbox registers or the FIFO data
channel, or a user can define and enable one or more
of the four Pass-Thru data channels. S5335 Bus Mas-
ter or DMA data transfers to and from the PCI Local
bus are performed through the FIFO data channel
under either Host or Add-On software control or Add-
On hardware control using dedicated S5335 signal
pins.
PCI Configuration Registers
All PCI compliant devices are required to provide a
group of Configuration Registers for the host system.
These registers are polled during power up initializa-
tion and contain specific device and add-in card
product information including Vendor ID, Device ID,
Revision and the amount of memory required for prod-
uct operation. The S5335 can either load these
registers with default values or initialize them from an
external non-volatile memory area called ‘Configura-
tion Space’. The S5335 can accommodate a total of
256 bytes of external memory for this purpose. The
first 64 bytes is reserved for user defined configuration
data which is loaded into the PCI Configuration Regis-
ters during power-up initialization. The remaining 192
bytes may be used to implement an Expansion BIOS
or contain add-in card POST code. Table 1 shows all
the S5335 PCI Configuration Registers.
The S5335 signal pins are shown in Figure 3. The PCI
Local Bus signals are detailed on the left side; Add-On
Local Bus signal are detailed on the right side. All
additional S5335 device control signals are shown on
the lower right side.
The S5335 supports a two wire serial nvRAM bus and
a byte-wide EPROM/FLASH bus. This allows the
designer to customize the S5335 configuration by
loading setup information on system power-up.
AMCC Confidential and Proprietary
DS1657 13
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
