Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 81. Synchronous FIFO Register Burst Read Access Example ................................................................. 133
Figure 82. Synchronous FIFO Register Burst RDFIFO# Access Example .......................................................... 134
Figure 83. Single Cycle Pass-Thru Write ............................................................................................................. 144
Figure 84. Single Cycle Pass-Thru Write with PTADR# ...................................................................................... 145
Figure 85. Single Cycle Pass-Thru Read with PTADR# ...................................................................................... 149
Figure 86. Pass-Thru Burst Write ........................................................................................................................ 149
Figure 87. Pass-Thru Burst Writes Controlled by PTRDY# ................................................................................. 150
Figure 88. Pass-Thru Burst Read ........................................................................................................................ 152
Figure 89. PCI Burst Read Controlled by PTRDY# .............................................................................................. 154
Figure 90. Target Requested Retry on the First PCI Data Phase ........................................................................ 156
Figure 91. Target Requested Retry after the First Data Phase of a Burst Operation .......................................... 157
Figure 92. Pass-Thru Signals after a Target Requested Retry ............................................................................ 158
Figure 93. Pass-Thru Write to an 8-bit Add-On Device ........................................................................................ 160
Figure 94. PCI Clock Timing ................................................................................................................................ 166
Figure 95. PCI Output Timing .............................................................................................................................. 167
Figure 96. PCI Input Timing ................................................................................................................................. 167
Figure 97. Add-On Clock Timing .......................................................................................................................... 168
Figure 98. Pass-Thru Clock Relationship to PCI Clock ........................................................................................ 168
Figure 99. Synchronous RDFIFO# Timing ........................................................................................................... 169
Figure 100. Synchronous WRFIFO# Timing ........................................................................................................ 170
Figure 101. Asynchronous RD# FIFO Timing ...................................................................................................... 171
Figure 102. Asynchronous WR# FIFO Timing ..................................................................................................... 172
Figure 103. Synchronous RD# FIFO Timing ........................................................................................................ 173
Figure 104. Synchronous RD# FIFO Timing ........................................................................................................ 174
Figure 105. Synchronous WR# FIFO Timing ....................................................................................................... 175
Figure 106. Synchronous Multiple WR# FIFO Timing .......................................................................................... 176
Figure 107. Pass-Thru Data Register Read Timing ............................................................................................. 178
Figure 108. Pass-Thru Data Register Write Timing ............................................................................................. 178
Figure 109. Pass-Thru Status Indicator Timing ................................................................................................... 179
Figure 110. nv Memory Read Timing ................................................................................................................... 180
Figure 111. nv Memory Write Timing ................................................................................................................... 180
Figure 112. IRQ# Interrupt Output Timing ........................................................................................................... 181
Figure 113. Mailbox 4, Byte 3 Direct Input Timing ............................................................................................... 181
Figure 114. S5335 Pinout and Pin Assignment - 176 LQFP (Low Profile Quad Flat Package) ........................... 182
Figure 115. Package Physical Dimensions - 176 LQFP ...................................................................................... 183
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