Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Table 50. Add-On General Control/Status Register (Continued)
Bit
Description
6
PCI to Add-On Transfer Count Equals Zero (RO). This bit as a one signifies that the read transfer count is all zeros.
Only when Add-On initiated bus mastering is enabled.
5
4
3
2
1
0
PCI to Add-On FIFO Empty. This bit is a 1 when the PCI to Add-On FIFO is empty.
PCI to Add-On FIFO 4+ spaces. This bit is a 1 when there are four or more open spaces in the PCI to Add-On FIFO.
PCI to Add-On FIFO Full. This bit is a 1 when the PCI to Add-On FIFO is full.
Add-On to PCI FIFO Empty. This bit is a 1 when the Add-On to PCI FIFO is empty.
Add-On PCI FIFO 4+ words. This bit is a 1 when there are four or more full locations in the Add-On to PCI FIFO.
Add-On to PCI FIFO Full. This bit is a 1 when the Add-On to PCI FIFO is full.
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