Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Table 45. Interrupt Control/Status Register
Bit
Description
31:24 FIFO and Endian Control.
23
Interrupt asserted. This read only status bit indicates that one or more of the four possible interrupt conditions is
present. This bit is nothing more than the ORing of the interrupt conditions described by bits 19 through 16 of this
register.
22
21
Reserved. Always zero.
Target Abort. This bit signifies that an interrupt has been generated due to the S5335 encountering a target abort
during a PCI bus cycle while the S5335 was the current bus master. This bit operates as read or write one clear. A
write to this bit with the data of “one” will cause this bit to be reset, a write to this bit with the data of “zero” will not
change the state of this bit.
20
19
Master Abort. This bit signifies that an interrupt has been generated due to the S5335 encountering a Master Abort
on the PCI bus. A master abort occurs when there is no target response to a PCI bus cycle. This bit operates as
read or write one clear. A write to this bit with the data of “one” will cause this bit be reset, a write to this bit with the
data of “zero” will not change the state of this bit.
Read Transfer Complete. This bit signifies that an interrupt has been generated due to the completion of a PCI bus
master operation involving the transfer of data from the PCI bus to the Add-On. This interrupt will occur when the
Master Read Transfer Count register reaches zero. This bit operates as read or write one clear. A write to this bit
with the data of “one” will cause this bit to be reset; a write to this bit with the data of “zero” will not change the state
of this bit.
18
Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completion of a PCI bus
master operation involving the transfer of data to the PCI bus from the Add-On. This interrupt will occur when the
Master Write Transfer Count register reaches zero. This bit operates as read or write one clear. A write to this bit
with the data of “one” will cause this bit to be reset; a write to this bit with the data of “zero” will not change the state
of this bit.
17
16
Incoming Mailbox Interrupt. This bit is set when the mailbox selected by bits 12 through 8 of this register are written
by the Add-On interface. This bit operates as read or write one clear. A write to this bit with the data of “one” will
cause this bit to be reset; a write to this bit with the data as “zero” will not change the state of this bit.
Outgoing Mailbox Interrupt. This bit is set when the mailbox selected by bits 4 through 0 of this register is read by the
Add-On interface. This bit operates as read or write one clear. A write to this bit with the data of “one” will cause this
bit to be reset; a write to this bit with the data of “zero” will not change the state of this bit.
15
14
Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the read transfer count
reaches zero. This bit is read/write.
Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the write transfer count
reaches zero. This bit is read/write.
13
12
Reserved. Always zero.
Enable incoming mailbox interrupt. This bit allows a write from the incoming mailbox register identified by bits 11
through 8 to produce a PCI interface interrupt. This bit is read/write.
11:10 Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes is to be the source for
causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and
[11]b selects mailbox 4. This field is read/write.
9:8
Incoming Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits 10 and 11 above
is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects
byte 3. This field is read/write.
7:5
Reserved, Always zero.
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