Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Table 45. Interrupt Control/Status Register (Continued)
Bit
Description
4
Enable outgoing mailbox interrupt. This bit allows a read by the Add-On of the outgoing mailbox register identified by
bits 3 through 0 to produce a PCI interface interrupt. This bit is read/write.
3:2
Outgoing Mailbox Interrupt Select. This field selects which of the four outgoing mailboxes is to be the source for
causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and
[11]b selects mailbox 4. This field is read/write.
1:0
Outgoing Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits 3 and 2 above is
to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte
3. This field is read/write.
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