Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Latency Timer Register (LAT)
The latency timer register has meaning only when this
controller is used as a bus master and pertains to the
number of PCI bus clocks that this master will be guar-
anteed. The nonzero value for this register is internally
decremented after this device has been granted the
bus and has begun to assert FRAME#. Prior to this
latency timer count reaching zero, this device can
ignore the removal of the bus grant and may continue
the use of the bus for data transfers.
Latency Timer
Register Name:
Address Offset:
Power-up value:
Boot-load:
0Dh
00h
External nvRAM offset 04Dh
Read/Write, bits 7:3; Read Only bits
2:0
Attribute:
8 bits
Size:
Figure 14. Latency Timer Register
7
6
5
4
3
2
0
1
0
0
0
Bit
X
X
X
X
X
Value
Latency Timer value (R/W)
# of clocks x 8
AMCC Confidential and Proprietary
DS1657 41
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
