Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Class Code Register (CLCD)
This 24-bit, read-only register is divided into three one-
byte fields: the base class resides at location 0Bh, the
sub-class at 0Ah, and the programming interface at
09h. The default setting for the base class is all ones
(FFh), which indicates that the device does not fit into
the thirteen base classes defined in the PCI Local Bus
Specification. It is possible, however, through use of
the external non-volatile memory, to implement one of
the defined class codes described in Table 22 below.
Class Code
Register Name:
Address Offset:
Power-up value:
Boot-load:
09h-0Bh
FF0000h
External nvRAM offset 049h-4Bh
Read Only
24 bits
Attribute:
For devices that fall within the seven defined class
codes, sub-classes are also assigned. Tables 23
through 35 describe each of the sub-class codes for
base codes 00h through 0Ch, respectively.
Size:
Figure 12. Class Code Register
@0Bh
@0Ah
@09h
(Offset)
0 (Bit)
7
0
7
0
7
Base Class
Sub-Class
Prog I/F
Table 22. Defined Base Class Codes
Base-Class
Description
00h
01h
Early, pre-2.0 PCI specification devices
Mass storage controller
Network controller
Display controller
02h
03h
04h
Multimedia device
Memory controller
Bridge device
05h
06h
07h
Simple communication controller
Base system peripherals
Input devices
08h
09h
0Ah
0Bh
0Ch
0D-FEh
FFh
Docking stations
Processors
Serial bus controllers
Reserved
Device does not fit defined class codes (default)
AMCC Confidential and Proprietary
DS1657 36
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
