Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 67. Synchronous FIFO or Pass-Thru Data Register Read
BPCLK
ADR[6:2]
Valid 1
Valid 2
BE[3:0]#
DQ[31:0]
Valid Data Out 1
Valid Data Out 2
RD#
RDFIFO#
SELECT#
Figure 68. Synchronous FIFO or Pass-Thru Data Register Write
BPCLK
ADR[6:2]
Valid 1
Valid 2
BE[3:0]#
DQ[31:0]
Valid Data In 1
Valid Data In 2
WR#
WRFIFO#
SELECT#
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