Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
PCI BUS INTERRUPTS
Data Sheet
phase, the SERR# signal is an open drain multi-
sourced, wire-ORed signal on the PCI bus. The S5335
drives SERR# low for one clock period when an
address phase error is detected. Once an SERR error
is detected by the S5335, the PCI Status register bit
14, System Error, is set and remains until cleared
through software or a hardware reset.
The S5335 controller is able to generate PCI bus inter-
rupts by asserting the PCI bus interrupt signal (INTA#).
INTA# is a multisourced, wire-ORed signal on the PCI
bus and is driven by an open drain output on the
S5335. The assertion and deassertion of INTA# have
no fixed timing relationship with respect to the PCI bus
clock. Once the S5335 asserts INTA#, it remains
asserted until the interrupt source is cleared by a write
to the Interrupt Control/Status Register (INTCSR).
The PERR# signal is similar to the SERR# with two
differences: it reports errors for the data phase and is
only asserted by the device receiving the data. The
S5335 drives this signal (removed from tri-state) when
it is the selected target for write transactions or when it
is the current master for bus read transactions. The
parity error conditions are only reflected by the PERR#
pin if the Parity Error Enable bit (bit 6) of the PCI Com-
mand register is set. Upon the detection of a data
parity error, the Detected Parity Error bit (bit 15) of the
PCI Status Register is set. Unlike the PERR# signal
pin, this Status bit sets regardless of the state of the
PCI Command register Parity Error Enable bit. An
additional status bit (bit 8) called “Data Parity
Reported” of the PCI Status register is employed to
report parity errors that occur when the S5335 is the
bus master. The “Data Parity Error Reported” status
requires that the Parity Error Enable bit be set in the
PCI Command register.
PCI BUS PARITY ERRORS
The PCI specification defines two error-reporting sig-
nals, PERR# and SERR#. These signals indicate a
parity error condition on the signals AD[31:0], C/
BE[3:0]#, and PAR. The validity of the PAR signal is
delayed one clock period from its corresponding
AD[31:0] and C/BE[3:0]# signals. Even parity exists
when the total number of ones in the group of signals
is equal to an even number. PERR# is the error-
reporting mechanism for parity errors that occur during
the data phase for all but PCI Special Cycle com-
mands. SERR# is the error-reporting mechanism for
parity errors that occur during the address phase.
The timing diagram in Figure 64 shows the timing rela-
tionships between the signals AD[31:0], C/BE[3:0]#,
PAR, PERR# and SERR#.
The assertion of PERR# occurs two clock periods fol-
lowing the data transfer. This two-clock delay occurs
because the PAR signal does not become valid until
the clock following the transfer, and an additional clock
is provided to generate and assert PERR# once an
error is detected. PERR# is only asserted for one
clock cycle for each error sensed. The S5335 only
qualifies the parity error detection during the actual
data transfer portion of a data phase (when both
IRDY# and TRDY# are asserted).
The S5335 asserts SERR# if it detects odd parity dur-
ing an address phase, if enabled. The SERR# enable
bit is bit 8 in the S5335 PCI Command Register. The
odd parity error condition involves the state of signals
AD[31:0] and C/BE[3:0]# when FRAME# is first
asserted and the PAR signal during the following
clock. If an error is detected, the S5335 asserts
SERR# on the following (after PAR valid) clock. Since
many targets may observe an error on an address
Figure 64. Error Reporting Signals
8
9
1
2
3
4
5
6
7
PCI CLOCK
FRAME
(I)
(I)
(T)
(I)
ADDR
A
DATA A
ADDR BB
DATA
BE's
AD[31:0]
(I)
CMD
AA
CMD BB
(I)
BYTEENABLES
C/BE[3:0]#
(T)
PAR
GOOD
A
GOOD
B
SERR#
(T)
(T)
ERROR
ERROR
GOOD
A
GOOD
B
PERR#
ERROR
ERROR
A
B
WRITE
TRANSACTION
READTRANSACTION
(I)=DRIVENBYINITIATOR
(T )=DRIVENBYTARGET
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