S4402/S4403
BiCMOS PLL CLOCK GENERATOR
PIN DESCRIPTIONS
Input Signals
REFCLK.
Frequency reference supplied by the user
that, along with the output tied to the FBCLK input,
determines the frequency of the FOUT0–FOUT3 out-
puts. Also replaces the VCO output when TSTEN is
high (after first divide-by-two stage in divider phase
control logic). See TSTEN.
FBCLK.
Feedback clock that, along with the
REFCLK input, determines the frequency of the
FOUT0–FOUT3 outputs. One output is selected to
feed back to this input. (See Table 3.)
DIVSEL.
Controls the divider circuit that follows the
VCO. When DIVSEL is low, the VCO frequency is
divided by four. When DIVSEL is high, the VCO fre-
quency is divided by eight. (See Tables 1 and 3.)
PHSEL0.
This input, along with PHSEL1, allows se-
lection of the phase relationship among the four
FOUT0–FOUT3 outputs. See Tables 2 and 3 for the
selection choices.
PHSEL1.
Along with PHSEL0, allows selection of the
phase relationship among the four FOUT0–FOUT3
outputs. See Tables 2 and 3 for the selection
choices.
OUTEN0.
Active Low. Output enable signal that con-
trols which outputs toggle. Controls the frequency
doubler output (X2FOUT) and the half-frequency out-
put (HFOUT).
OUTEN1.
Active Low. Output enable signal that con-
trols which outputs toggle. Controls the FOUT0–
FOUT3 outputs.
OUTEN2.
(S4403 only.) Active Low. Controls the
duplicate set of outputs to FOUT0–FOUT3
(FOUT0A, FOUT1A, FOUT2A, AND FOUT3A).
RESET.
Active Low. Initializes internal states for test
purposes.
TSTEN.
Active High. Allows REFCLK to drive the
divider phase adjust circuitry, after the first divide-by-
two stage. Therefore, REFCLK is divided by two in
the divide-by-four mode, and divided by four in the
divide-by-eight mode, and used to directly sequence
the outputs.
Output Signals
FILTER.
A tap between the analog output of the
phase detector and the VCO input. Allows a simple
external filter (a single resistor and one capacitor) to
be included in the PLL.
X2FOUT.
Provides a clock signal identical to the
FOUT0 output in the divide-by-four mode and twice
the FOUT0 frequency (maximum of 80 MHz) in the
divide-by-eight mode.
FOUT0.
Clock output.
FOUT1.
Clock output.
FOUT2.
Clock output.
FOUT3.
Clock output.
HFOUT.
Provides a clock signal in phase with the
FOUT0 output, but at half the FOUT0 frequency in
both the divide-by-four and divide-by-eight modes.
LOCK.
Goes high when REFCLK and FBCLK are
within 2–4 ns of each other, demonstrating that the
PLL is in lock.
FOUT0A.
(S4403 only.) Clock output—duplicates
FOUT0.
FOUT1A.
(S4403 only.) Clock output—duplicates
FOUT1.
FOUT2A.
(S4403 only.) Clock output—duplicates
FOUT2.
FOUT3A.
(S4403 only.) Clock output—duplicates
FOUT3.
Page 4
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
