欢迎访问ic37.com |
会员登录 免费注册
发布采购

S4402A-80 参数 Datasheet PDF下载

S4402A-80图片预览
型号: S4402A-80
PDF下载: 下载PDF文件 查看货源
内容描述: [Clock Generator, 80MHz, BICMOS, PQCC28, PLASTIC, LCC-28]
分类和应用: 时钟信息通信管理外围集成电路晶体
文件页数/大小: 13 页 / 151 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号S4402A-80的Datasheet PDF文件第2页浏览型号S4402A-80的Datasheet PDF文件第3页浏览型号S4402A-80的Datasheet PDF文件第4页浏览型号S4402A-80的Datasheet PDF文件第5页浏览型号S4402A-80的Datasheet PDF文件第6页浏览型号S4402A-80的Datasheet PDF文件第7页浏览型号S4402A-80的Datasheet PDF文件第8页浏览型号S4402A-80的Datasheet PDF文件第9页  
®
DEVICE SPECIFICATION
S4402/S4403
FEATURES
• Generates six clock outputs from 20 MHz to
80 MHz (the S4403 generates ten outputs and
HFOUT generates 10MHz to 40MHz)
• 21 selectable phase/frequency relationships for
the clock outputs
• Compensates for clock skew by allowing output
delay adjustment down to 3.125 ns increments
• TTL outputs have less than 400 ps maximum
skew
• Lock Detect output indicates loop status
• Internal PLL with VCO operating at 160 to
320 MHz
• Test Enable input allows VCO bypass for open-
loop operation in board test
• Maximum 1.0 ns of phase error (750 ps from
part to part)
• Proven 1.0 micron BiCMOS technology
• Single +5V power supply operation
• 28/44 PLCC packages
BiCMOS PLL CLOCK GENERATORS
APPLICATIONS
• CMOS ASIC Systems
• High-speed Microprocessor Systems
• Backplane Clock Deskew and Distribution
GENERAL DESCRIPTION
The S4402/S4403 BiCMOS clock generators allow
the user to generate multiphase TTL clocks in the
10–80 MHz range with less than 400 ps of skew. Use
of a single off-chip filter allows an entire 160–320
MHz phase-locked loop (PLL) to be implemented on-
chip. Divide-by-two and times-two outputs allow the
ability to generate output clocks at half, equal to, or
twice the reference clock input frequency. By using
the programmable divider and phase selector, the
user can select from up to 21 different output rela-
tionships. The outputs can be phase-adjusted in in-
crements as small as 3.125 ns to tailor the clocks to
exact system requirements.
Implemented in AMCC’s proven 1.0 micron BiCMOS
technology, the S4402 generates six TTL outputs,
while the S4403 provides those six plus four dupli-
cates (FOUT0A–FOUT3A) for a total of ten. Output
enables are provided for the various banks, allowing
clock control for board and system tests.
Figure 1. Clock Generator Block Diagram
REFCLK
PHASE
DETECTOR
CHARGE
PUMP
LOCK
NOTE: FOUT0A, FOUT1A,
FOUT2A, FOUT3A, and
OUTEN2 apply only to the
S4403.
FBCLK
FILTER
X2FOUT
VCO
÷2
HFOUT
I
0
I
1
MUX
TSTEN
SELECT
DIVIDER
AND
PHASE
CONTROL
LOGIC
FOUT0A
FOUT0
FOUT1A
FOUT1
Digital
+5V
0V
DIVSEL
PHSEL0
PHSEL1
RESET
FOUT3
FOUT2
FOUT2A
FOUT3A
Analog
+5V
0V
OUTEN0
OUTEN1
OUTEN2
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 1