®
DEVICE SPECIFICATION
&21),'(17,$/
Multi-Rate Performance Monitor with Forward Error Correction
S3062
Figure 4 Detailed Block Diagram
PTA
PINT
TXCLKP/N
2
Key:
main data path
clocks and timing
internal signals
I/O signals
PECLREF, DATAIN [15:0]
CLKIN P/N
2
FEC_RDIV
16
FEC_ERR,
RX_FEC_DLCK,
RX_FEC_DL
DeMUX1:2
Rx
Clock
Divider
differential &
Transmit
Timing
FEC decode
FEC_DEC
PCLK
32
PCS
32
PDAT[15:0]
PADD[10:0]
TCLK/2
Processor
Interface
(PIF)
32
PRW
PTS
ADDR,
DATA,
CTR
FIFO
PBDIP, PBURST
PM_CLK
(to all
blocks)
PASSTHRU Data
LOS Data Check
32
1 second clock
(to error counters)
LOS
OOF
LOF
Byte Align and
Frame Find/Check
Frame Indicator
GBE enable
Frame Counter
And Enables
FPOUTB
RATESEL[1:0]
Section Trace
Overhead locator pulses
(to all blocks)
ST message
(to PIF)
STS mode
(to all blocks)
B1ERR
DESCRBEN (RX_FEC_DL)
FPGASEL
Section BIP-8
Descrambler
B1 error counts
All-1s
B1
RX_OH
Mem A
648 x 16
RX_OH
Mem B
648 x 16
FPGA Mode / Serial Link Mode
_____________|______________
LOS, LOF
AIS-L MUX1
AIS_ON
/
\
AutoAIS
AUTOAIS
RX_OH_DATA7
RX_OH_DATA6
RX_OH_DATA5
RX_OH_DATA4
RX_OH_DATA3
RX_OH_DATA2
RX_OH_DATA1
RX_OH_DATA0
OH_CLK
/
/
/
/
/
/
/
/
RX_SOW
RX_LOW
SF, SD
BER
RX_OW _CLK
RX_OW _FP
RX_SDCC
RX_SDCC_CLK
RX_LDCC
RX_LDCC_CLK
TX_OW _CLK
TX_OW_FP
To PIF
Line BIP-8
Overhead Extract
State Machine
B2 error count
AIS_L, RDI_L,
12
Section/
Line OH
APS
K1/K2 inconsistency
S1 errors
Serializer
/
/
Synchronization
RX_OH_FP
SDCC, LDCC,
E1, E2
TX_OH_FP
/
/
TX_SDCC_CLK
TX_LDCC_CLK
Remote Error
Indication
REI_L error count
SDCC, LDCC,
E1, E2
TX_OH_DATA7
TX_OH_DATA6
TX_OH_DATA5
TX_OH_DATA4
TX_OH_DATA3
TX_OH_DATA2
TX_OH_DATA1
TX_OH_DATA0
TX_OH_INS
/
/
/
/
/
/
/
/
TX_SOW
TX_SOW_SEL
TX_LOW
TX_LOW_SEL
TX_SDCC
TX_SDCC_SEL
TX_LDCC
J0
Parallelizer
A1,A2,B1
Note that
B2
TX_OH
Mem A
648 x 16
TX_OH
Mem B
648 x 16
9
BLOCKBIP and
XORBIP share
the same pins as
TX_FEC_DLCK
and TX_FEC_DL
FIXSOH
FIXB2
Overhead MUX
OH Insert MUX
Section Trace
TX_LDCC_SEL
SOH/LOH
& Control
message
(from PIF)
/
Overhead Insert
State Machine
MEMOH
To Section
BLOCKBIP,
XORBIP
Line
BIP-8
From/To PIF
BIP-8
All-1’s
FIXB2
Transmit Access
Overhead Insert
Control Memory
81 x 16
Control Memory
81 x 16
AIS_ON
AIS-L MUX2
Framing,
Section
BIP-8
FIXSOH
DATAAIS
Scrambler
SCRBEN (RX_FEC_DLCK)
Note that the
gigabit ethernet
errors share
the same pins
as LOS, OOF
and LOF.
All-0’s
Data Off MUX
DATAOFF
PASSTHRU Data
GBE enable
PASSTHRU MUX
PASSTHRU
TM
INV_CODE
DISP_ERR
Gigabit
Ethernet
Monitor
32
to internal test circuitry
error
injection
SYNC_LOSS
differential &
FEC encode
TCK
TMS
TDI
FEC_ENC,
TX_FEC_DL
TX_FEC_DLCK
Test Access
Port
32
Tx Clock
Divider
TDO
MUX2:1
TRSTB
16
2
to all blocks
RESETB
DATAOUT[15:0]
CLKOUTP/N
FEC_TDIV
Applied Micro Circuits Corporation
6290 Sequence Drive, San Diego, CA
(858) 450 9333
Revision D
CONFIDENTIAL
November 29, 2000
Page 13 of 136
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
