®
DEVICE SPECIFICATION
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Multi-Rate Performance Monitor with Forward Error Correction
S3062
2.3 SONET/SDH Application Overview
In SONET/SDH mode, all received section and line overhead bytes are captured and placed in a memory. The memory is accessible
from either a processor or an FPGA. The overhead bytes that are defined by the SONET/SDH standards are also monitored for
errors and performance monitoring (PM) statistics. The results are accessible from the processor or FPGA interface.
In addition to being stored in an accessible memory, received section overhead is managed as follows:
A1 and A2 bytes are checked for framing and byte alignment.
J0 byte is monitored for section trace messages.
B1 byte is monitored for bit interleaved parity errors, which are accumulated over 1 second periods.
E1 byte is optionally serialized and output on an I/O pin.
D1-3 bytes are optionally serialized and output on an I/O pin.
The data can be descrambled in accordance with SONET/SDH standards.
Section errors -- LOS, LOF, OOF and B1 -- are output on I/O pins and are available to the processor and FPGA interfaces.
In addition to being stored in an accessible memory, received line overhead is managed as follows:
B2 byte is monitored for bit interleaved parity errors, which are accumulated over 1 second periods.
K1 and K2 bytes are monitored for new or inconsistent values. K2 is also monitored for line AIS and RDI.
D4-12 bytes are optionally serialized and output on an I/O pin.
S1 byte is monitored for inconsistent values and for mismatches with a software programmable value.
M1 byte is monitored for REI errors, which are accumulated over 1 second periods.
E2 byte is optionally serialized and output on an I/O pin.
Line error indicators – line AIS, line RDI, line REI, B2, signal fail, signal degrade, K1, K2 and S1 changes are only accessible via
the processor or FPGA interfaces; they are not output on I/O pins.
All transmitted section and line overhead bytes can be written through the FPGA or processor interface. In addition, data
transmission can be modified as follows:
Framing bytes can be regenerated with values A1 = F6h and A2 = 28h.
J0 byte may be filled with section trace bytes from a memory.
B1 and B2 bytes can be recalculated.
E1, D1-3, D4-12 and E2 bytes can be sourced, serially from S3062 I/O pins.
The data can be scrambled in accordance with SONET/SDH standards.
Line AIS can be activated automatically when LOS or LOF conditions are detected, or the user may force the transmitter to
output line AIS.
The entire data stream can be turned off (all zeros output).
The SONET/SDH application is designed to monitor incoming SONET/SDH data streams and optionally modify them. It can also
be used as a SONET/SDH generator. The S3062 transmit clock (TXCLKP/N) will generate correct section (regenerator) overhead
and line AIS if the receive clock (CLKINP/N) is absent. If the receive clock is present, any data format may be turned into
SONET/SDH frame. The frame counter does not need to find byte alignment to begin running. They start counting after the S3062
comes out of reset. To complete the frame, correct section and line overhead may be inserted from the TX_OH or any other S3062
method. When using the S3062 as a SONET/SDH generator with the receive and transmit clocks present, random data should be
avoided at the input due to possibility of false framing, which would cause the internal framing counters to jump.
To select the SONET/SDH mode, choose the desired rate by using the RATESEL[1:0] pins, or by writing the corresponding register
bits. Differential encoding and decoding, as well as forward error correction, may also be implemented in this mode.
NOTE: Pass-through mode has priority over RATESEL and will negate any RATESEL selections if pass-through mode is enabled.
Applied Micro Circuits Corporation
6290 Sequence Drive, San Diego, CA
(858) 450 9333
Revision D
CONFIDENTIAL
November 29, 2000
Page 12 of 136
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
