OC-48 APPLICATION NOTE WITH AMAZON/S3059/S3056 AND SUMITOMO FIBER OPTIC
Parts List
The following is a parts list that is a recommendation to the designer to implement the circuit in Figures 1 and 2.
QTY
Part # or Equivalent Description
2
20
2
40
2
1
4
6
2
Resistor, 56 Ω, 10%, 1/8W, 805 or 603 package size
Resistor, 100 Ω, 10%, 1/8W, 805 or 603 package size
Resistor, 180 Ω, 10%, 1/8W, 805 or 603 package size
Resistor, 200 Ω, 10%, 1/8W, 805 or 603 package size
Resistor, 390 Ω, 10%, 1/8W, 805 or 603 package size
Resistor, 510 Ω, 10%, 1/8W, 805 or 603 package size
Resistor, 1kΩ, 10%, 1/8W, 805 or 603 package size
Capacitor, 0.1 µF, 10%, X7R, 16V, Surface Mount package
Capacitor, 10 µF, 10%, X7R, 16V, Surface Mount package
Multi-Rate (OC-48/24/12/3/GBE) SONET/SDH/ATM Tranceiver
SONET/SDH Clock Recovery Unit
1
1
S3059
S3056
1
1
S4801 AMAZON
SDM7128-XC
AMCC OC-48 POS/ATM/SONET Mapper
Sumitomo 5V Fiber Optic 1 x 9 Transceiver
1
LVPECL Oscillator, +3.3V at 155.52 MHz
1
MMBT3904LTI
NPN Transistor, 2N3904
Theory Of Operation
5. The 16-bit parallel data is output from the AMCC
AMAZON S4801 into the S3059 parallel data in-
put bus (PINP/N[15:0]) and is sampled by the
Parallel Input Clock (PICLKP/N) of the S3059.
This clock is generated by the S3059 Parallel
Clock (PCLKP/N) which is fed into the AMCC
AMAZON S4801 as the transmit clock
(TX_SONETCLK) and then back into the
PICLKP/N input of the S3059.
1. The S3056 extracts the clock and re-times the
data from the received differential CML serial
data input (SERDATIP/N) coming from the fiber
optic receiver when the signal detect (SDN) is a
PECL Low level. When signal detect (SDN) is at a
PECL High level, the Phase Lock Loop (PLL) will
be forced to lock to the PECL Reference Clock
(REFCLKP/N). When the transmit PLL is locked
to the SERDATIP/N input the Lock Detect
(LOCKDET) TTL output goes High.
6. The 16-bit parallel data is then converted into bit-
serial data and output through the Transmit Serial
Data (TSDP/N) connections to the Sumitomo fiber
optic transmitter (SDM7128-XC).
2. The S3059 receives the OC-48 (2.488 Gbit/s)
scrambled NRZ data signals on the serial data
stream (RSDP/N) CML inputs. These inputs are
clocked into the S3059 by the Receive Serial
Clock (RSCLKP/N) CML inputs. This clock is
used by the receive section as the master clock
for all deserialization functions.
7. If the incoming serial-bit data stream is lost (when
SDN is High) the lock detect circuit internal to the
S3056 substitutes the external reference clock for
the missing data stream clocking signal. This sub-
stitution of reference timing source is helpful to
supply a continuous timing signal for the up-
stream devices and system operation even
though valid received data does not exist. This
switch over is a smooth transition with no notice-
able phase shift.
3. The AMCC AMAZON S4801 does not assume
that the parallel input data are byte aligned. The
S4801 device will align to the incoming data.
4. The serial-bit data stream is then converted into a
16-bit parallel data format for output onto the Par-
allel Output data bus (POUTP/N[15:0]). The 16-
bit parallel data is clocked out of the S3059 and
into the AMCC AMAZON S4801 with the Parallel
Output Clock (POCLKP/N).
3
March 26, 2001 / Revision 1.01
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
