OC-48 APPLICATION NOTE WITH AMAZON/S3059/S3056 AND SUMITOMO FIBER OPTIC
Figure 2. S3059 Transceiver, S3056 CRU, Sumitomo SDM7128-XC Fiber Optic Transceiver and
AMCC AMAZON S4801 POS/ATM SONET Mapper Block Diagram
+5 V Part
+3.3 V Part
+3.3 V Part
+3.3 V Part
10 µF
56 Ω
56 Ω
KILLRXCLK
POUTP[15:0]
"Logic 1"
CAP1 CAP2
Zo = 50 Ω
RX_DATA[15:0]P
RX_DATA[15:0]N
0.1 µF
200 Ω
200 Ω
RD
SERDATIP/N
100Ω
POUTN[15:0]
RSDP/N
RDb
SERDATOP/N
0.1 µF
100 Ω
390 Ω
3.3 V
390 Ω
POCLKP
POCLKN
RX_SONETCLK_P
RX_SONETCLK_N
200 Ω
200 Ω
AMCC S3056
RSCLKP/N
1 kΩ
510 Ω
SERCLKOP/N
100 Ω
SDN
"LOGIC 1"
RATESEL0
SDLVPECL
N/C
"LOGIC 1"
"LOGIC 1"
RATESEL1
REFSEL
SD
1 kΩ
AMCC
S3059
SDTTL
100 Ω
LOCKDET
N/C
BYPASSCLKP/N
RATESEL0
RATESEL1
155MCKN
Sumitomo
Fiber Optic
Transceiver
Module
Line
Side
Interface
AMCC
AMAZON
S4801
"LOGIC 1"
"LOGIC 1"
200 Ω
1 x 9
SDM7128-XC
155MCKP
TX_SONETCLK_OUTP
TX_SONETCLK_OUTN
TX_SONETCLKP
PICLKP
200 Ω
100 Ω
PICLKN
PCLKP
19MCK
0.1 µF
200 Ω
200 Ω
PCLKN
TX_SONETCLKN
REFCLKP/N
100 Ω
Zo = 50 Ω
155.52 MHZ
Oscillator
LVPECL
0.1 µF
180 Ω
16
PINP[15:0]
TX_DATA[15:0]P
TX_DATA[15:0]N
"LOGIC 0"
"LOGIC 0"
"LOGIC 0"
"LOGIC 1"
BYPASS
RLPTIME
TESTEN
100 Ω
16
PINN[15:0]
PHERRP
DLEB
LLEB
200 Ω
200 Ω
PHERRN
PHINITN
"LOGIC 1"
SLPTIME
"LOGIC 0"
"LOGIC 0"
SQUELCH
100 Ω
PHINITP
RSTB
TSCLKP/N
TSDP
0.1 µF
TD
100 Ω
TDb
TSDN
CAP1
Zo = 50 Ω
RSTB
0.1 µF
CAP2
1 kΩ
1 kΩ
RESET
10 µF
RESET
2
March 26, 2001 / Revision 1.01
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
