S3053
2.488 GBPS – 2.7 GBPS QUAD MUX WITH FAN OUT BUFFERS
Table 2. Pin Assignment and Descriptions
Pin Name
Level
Int.
Biased
Diff.
LVPECL
Int.
Biased
Diff.
LVPECL
LVTTL
I/O
Pin#
42
41
50
51
29
28
37
38
43
36
17
18
23
22
4
5
10
9
49
30
6, 8, 19,
20, 21,
32, 34,
45, 46,
47,
15
25
2
12
1, 7, 13,
14, 26,
27, 31,
33, 35,
39, 40,
44, 48,
52,
Output
GND
16
24
3
11
Description
Differential inputs to the multiplexer.
INA0P
INA0N
INA1P
INA1N
IND0P
IND0N
IND1P
IND1N
SELA
SELD
OUTB0P
OUTB0N
OUTB1P
OUTB1N
OUTC0P
OUTC0N
OUTC1P
OUTC1N
SELB
SELC
VCC
I
Differential inputs to the multiplexer.
I
I
A Low selects IN0. When High, this signal selects IN1.
Serial output from Mux B.
Diff.
CML
O
Serial output from Mux C.
Diff.
CML
O
LVTTL
I
A Low selects Mux A output. When High, this signal selects the
Mux D output.
Power Supply. 3.3V nominal.
VSWB0
VSWB1
VSWC0
VSWC1
VEE
Voltage Swing Control pin.
Analog
I
Ground.
VEEB0
VEEB1
VEEC0
VEEC1
Ground for B0, B1, C0, C1.
4
October 10, 2000 / Revision D
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
