E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B OVERVIEW
The S3031B transceiver can be used to implement the
front end of STS-3, OC-3 or E4 equipment. The block
diagram in Figure 9 shows the basic operation of the
chip.
When the S3031B is operating in the nibble parallel
mode, the transmitter VCO is synchronized to the 38.88
MHz nibble clock as both the reference clock and the
data transfer clock. If the serial input is selected as the
transmitter data source the VCO will be synchronized
directly to the incoming data. Serial operation of the
S3031B transmitter section is possible with either the
38.88 MHz or 19.44 MHz reference oscillator. In the
absence of incoming serial data the transmitter section
will operate as a clock synthesizer. The receiver section
performs clock recovery by synchronizing its on-chip
VCO directly to the incoming data stream.
In E4 operation, the 34.816 MHz REFCLK is used as the
nibble clock. Thus in Nibble parallel mode, the S3031B
transmitter section supports unscrambled E4 operation.
If serial mode is selected, the NRZ E4 data must be
scrambled to allow the PLL to lock onto the data transi-
tions.
The S3031B provides a PECL output for an optical
interface and two transformer driver outputs for an
electrical interface. One of these drivers is a monitor
output. The S3031B provides a PECL input for an
optical interface and an analog input for an electrical
interface.
The transformer driver outputs are separately enabled.
Status outputs detect the disabled, stuck at 1, stuck at
0, and non-CMI states to qualify the transformer driver
outputs.
The CMI outputs, analog equalizer input section, and
PLL sections are independently powered for isolation
and for power savings when the device is used in single
function applications.
S3031B
S3031B TRANSMITTER
ARCHITECTURE/FUNCTIONAL DESIGN
Transmitter Operation
The S3031B chip’s transmitter section performs the last
stages of digital processing of a transmit SONET STS-3
or ITU-T E4 serial or 4-bit nibble parallel data stream.
Clock Recovery
If the serial input data has been selected, and serial
data is present at the TSDATIP/N inputs, the clock is
recovered from the serial data stream at 139.264 MHz
or 155.52 MHz and synthesized to 278.528 MHz or
311.04 MHz to CMI encode the incoming data.
In clock recovery mode, the transmitter PLL continues
to monitor the reference clock with respect to the VCO
and the activity of the serial data input. The transmitter
PLL will re-lock to the reference clock under the follow-
ing conditions:
1. If the serial data inputs contains insufficient transition
density (run length greater than 100 to 200 bit times).
2. If the VCO drifts away from the local reference clock
by more than 1000 ppm.
If either XFRMENA or XFRMENB are enabled (logic
Low) the density or frequency error defined above will
set the appropriate status (XFRMSTATA and/or
XFRMSTATB) to the low or fault state.
The selected drive status bits will return to the High or
clear state and the PLL will again lock to the data if the
serial data contains sufficient transition density (less
than 100 to 200 bit times between rising edges), and the
serial clock is within 250 ppm of the reference clock
determined frequency.
Optical and Electrical Interfaces
The digital data outputs (TSDATOP/N) are the PECL
outputs for an optical interface and are to be con-
nected to an electrical to optical converter, as shown
in Figure 17. This data is also routed to two on-chip
transformer drivers and sent out on XFRMDRVA and
XFRMDRVB to drive the transformers of the electri-
cal interface, as shown in Figure 19. These outputs
are shut off when the reset is active, XFRMEN is active,
or when the chip is in NRZ mode and the data inputs
are in the logic zero state. The electrical characteristics
for the transformer drivers are shown in Table 9.
August 19, 1999 / Revision D
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
