E4/STM-1/OC-3 ATM TRANSCEIVER
Table 2. Transmitter Input Pin Assignment and Description
Pin Name
TSTCLKEN
Level
TTL
I/O
I
Pin #
26
Description
S3031B
Test Clock Enable. Active High. Enables the TESTCLK clock to
be used in place of the VCO for testing. Allows a means of testing
the functions of the chip without the use of the PLL.
Diagnostic Line Code Violation. Set High to force a CMI line code
violation. DLCV is only active in CMI mode. DLCV is sampled on
the falling edge of TSCLKOP. DLCV does not affect XFRMSTATB
or XFRMSTATB.
CMI Select. Used to select a CMI or NRZ. A logic High selects
CMI mode. A logic Low selects NRZ mode. Both the TSDATOP/N
and the XFRMDRV outputs are controlled by CMISEL.
Transmitter Reset. Active Low. Initializes the device to a known
state. Serial data outputs are held to zero, and the Transformer
Driver and Status outputs are forced Low.
Loop Filter Capacitor Network. The loop filter capacitor network is
connected to these pins. The capacitor value should be 1.0 µF
±10%, X7R dielectric. The resistors should be 100
Ω
for serial
mode and 1000
Ω
for nibble mode operation. See Figure 18.
Transformer Driver Enable. Used to enable the transformer driver
output. A logic Low enables XFRMDRVA. A logic High turns off
the transformer driver output.
Transformer Driver Enable.Used to enable the transformer driver
output. A logic Low enables XFRMDRVB. A logic High turns off
the transformer driver output.
Serial Data Enable. Used to enable the transmit serial data
outputs. A logic Low enables TSDATOP/N. A logic High turns off
the serial data outputs.
Parallel Data Input. A 38.88 Mbyte/sec 4-bit wide Nibble aligned
to the REFCLK reference clock. REFSEL and SERDSEL must
both be at logic Low for transmitter operation with the nibble
inputs.
Transmit Serial Data In. The transmit clock is derived from
transitions on these inputs when SERDSEL is High. No phase
relationship to REFCLK is required. Either 19.44 MHz or 38.88
MHz reference operation may be selected. SERDSEL must be at
logic High for transmitter operation with the serial data input.
DLCV
Single-
ended
PECL
TTL
I
86
CMISEL
I
27
TXRSTB
TTL
I
97
CAP1
CAP2
I
21
22
XFRMENA
TTL
I
92
XFRMENB
TTL
I
94
SERDATEN
TTL
I
8
PIN3
PIN2
PIN1
PIN0
TSDATIP
TSDATIN
TTL
I
1
100
99
98
15
16
Diff.
PECL
I
August 19, 1999 / Revision D
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
