S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
S3029 Transceiver Pin Assignment and Descriptions
Pin Name
REFCKINP/N
Level
Diff.
LVPECL
I/O
I
Pin #
53,54
Description
Reference Clock. 19.44 or 51.84 MHz input used to generate
the 155 MHz transmit clock. This input is also used as the
reference for the internal bit clock in the absence of serial data
or during reset in clock recovery mode.
Serial Data In. Clock is recovered from the transitions on these
inputs.
SERDATIP/N0
SERDATIP/N1
SERDATIP/N2
SERDATIP/N3
TSTCLKEN
Diff.
LVPECL
I
1,2
7,8
15,16
22,21
3
LVTTL
I
Test Clock Enable. Active High. Used during production test to
bypass the VCO in the PLL. Tie to ground for normal operation.
Signal Detect. Active High. A single-ended 10K ECL input to be
driven by the external optical receiver module to indicate
detection of received optical power. When SD is inactive, the
data on the Serial Data In (SERDATIP/N) pins will be internally
forced to a constant zero, LOCKDET forced low, and the PLL
forced to lock to the REFCK input. When SD is active, data on
the SERDATIP/N pins will be processed normally. This pin has
an internal 1K
Ω
pull-down.
Lock to Reference. Active Low. When active, this input will force
the CRU to lock to the local reference clock. This input has an
internal 1K pull-up and may be left unconnected if not used.
Reference Select. This input selects the frequency of the
REFCKIN/P. (See Table 1).
Lock Detect. Active High. Clock recovery indicator. Set high
when the internal clock recovery has locked onto the incoming
datastream. LOCKDET is an asynchronous output. This output
is deasserted when LCKREFN is low, or when SD is low; in
which case the PLL locks to the reference clock. When the data
rate of the SERDATIP/N input is not within the capture range of
the PLL, the LOCKDET output will toggle until proper data is
restored.
Serial Data Out. This signal is the delayed version of the
incoming data stream (SERDATI) updated on the falling edge of
Serial Clock Out (SERCLKOP).
Serial Clock Out. This signal is phase aligned with Serial Data
Out (SERDATO) when Lock Detect (LOCKDET) is High. When
Lock Detect is Low, Serial Clock Out is synchronous with
Reference Clock (REFCKIN).
Transmit Clock Out. This is a 155 MHz clock which can be used
by the controller as a clock source for the transmitter logic.
SD0
SD1
SD2
SD3
LVPECL
I
56
55
52
51
LCKREFN0
LCKREFN1
LCKREFN2
LCKREFN3
REFSEL
LVTTL
I
64
63
60
59
6
LVTTL
I
LOCKDET0
LOCKDET1
LOCKDET2
LOCKDET3
LVTTL
O
9
14
17
20
Diff.
SERDATOP/N0
SERDATOP/N1 LVPECL
SERDATOP/N2
SERDATOP/N3
SERCLKOP/N0
SERCLKOP/N1
SERCLKOP/N2
SERCLKOP/N3
TXCLKOP/N
Diff.
LVPECL
O
44,43
40,39
30,29
26,25
46,45
38,37
32,31
24,23
50,49
O
Diff.
LVPECL
O
4
February 19, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
