S3029
Figure 2. Functional Block Diagram
REFSEL
REFCKINP
REFCKINN
TSTCLKEN
SD0
LCKREFN0
REFCLK
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
PLL CLOCK
MULTIPLIER
155 MHz CLK
TXCLKOP
TXCLKON
LOCKDET0
SERDATIP0
SERDATIN0
PLL CLOCK
RECOVERY
BITCLK
D
Q
QN
SERDATOP0
SERDATON0
SD1
LCKREFN1
REFCLK
SERCLKOP0
SERCLKON0
LOCKDET1
SERDATIP1
SERDATIN1
PLL CLOCK
RECOVERY
BITCLK
D
Q
QN
SERDATOP1
SERDATON1
SD2
LCKREFN2
REFCLK
SERCLKOP1
SERCLKON1
LOCKDET2
SERDATIP2
SERDATIN2
PLL CLOCK
RECOVERY
BITCLK
D
Q
QN
SERDATOP2
SERDATON2
SD3
LCKREFN3
REFCLK
SERCLKOP2
SERCLKON2
LOCKDET3
SERDATIP3
SERDATIN3
PLL CLOCK
RECOVERY
BITCLK
D
Q
QN
SERDATOP3
SERDATON3
SERCLKOP3
SERCLKON3
2
February 19, 1999 / Revision B