APPLICATION NOTE
S3017 WITH DATA CLOCK SYNCHRONOUS TO REFERENCE CLOCK
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3017/S3018
INTRODUCTION
The connections required to implement the design are
shown in Figure 15, and the timing specifications are
shown in Figure 16. The setup and hold times for the
PICLK to the data must be met by the controller ASIC.
We recommend latching the data on the falling edge of
the output reference clock in order to meet the required
specifications.
In some applications it is necessary to “forward clock”
the data in a SONET/SDH system. In this application
the reference clock from which the high speed serial
clock is synthesized and the parallel data clock both
originate from the same (usually TTL/CMOS) clock
source. This application note explains how the AMCC
S3017 can be configured to operate in this mode.
Possible Problems
Clock Control Logic Description
In order to meet the jitter generation specifications
required by SONET, the jitter of the reference clock
must be minimized. It may be difficult to meet the
SONET jitter generation specifications using a refer-
ence clock input with a TTL reference source.
The timing control logic in the S3017 automatically
generates an internal load signal which has a fixed
relationship to the reference clock. The logic takes into
account the variation of the reference clock to the
internal load signal over temperature and voltage.
Figure 15. S3017 with Data Clocked by Reference Clock
TTL/PECL
Converter
tpd <3.5 ns
PECL
2
ASIC
REFCLK
PICLK
Output
Reference
Clock
Serial Data
S3017
8
Output
Data
Data
DATAIN[7:0]
Figure 16. Data Timing with Respect to PICLK
PICLK
DATAIN [7:0]
t
t
t
= 2 ns
= 1 ns
su
su
h
t
h
20
December 10, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
